Miscellaneous active electrical nonlinear devices – circuits – and – Specific identifiable device – circuit – or system – With specific source of supply or bias voltage
Reexamination Certificate
2001-05-15
2002-10-08
Cunningham, Terry D. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Specific identifiable device, circuit, or system
With specific source of supply or bias voltage
Reexamination Certificate
active
06462610
ABSTRACT:
TECHNICAL FIELD
The present invention is related generally to semiconductor integrated circuits, and more specifically, to a circuit and method for reducing subthreshold leakage currents of transistors forming an integrated circuit.
BACKGROUND OF THE INVENTION
A typical integrated circuit includes numerous transistors formed in a semiconductor substrate and interconnected to perform desired functions. In many integrated circuits, such as semiconductor memories or microprocessors, the transistors formed in the semiconductor substrate are typically metal oxide semiconductor (“MOS”) transistors having source, drain, and gate regions formed in the semiconductor substrate. Each MOS transistor has a threshold voltage V
T
corresponding to the gate-source voltage that must be exceeded to turn ON the transistor and allow current flow from the source region to the drain region of the transistor. In an ideal MOS transistor, for gate-to-source voltages less than the threshold voltage V
T
, no current flows between the source and drain regions. In an actual MOS transistor, however, there is current flow between the source and drain regions when the gate-to-source voltage is less than the threshold voltage V
T
. This current which flows for gate-to-source voltages less than the threshold voltage V
T
is known as the subthreshold leakage current of the transistor.
Due to the subthreshold leakage currents of transistors forming the integrated circuit, a significant amount of power may be consumed by the integrated circuit even when all of the MOS transistors are turned OFF. This is true since millions of transistors may comprise an integrated circuit, and, while the subthreshold leakage current of an individual transistor is negligible, in the aggregate such subthreshold leakage currents can result in significant power consumption.
One way to lower the subthreshold leakage current of a MOS transistor is to increase the threshold voltage V
T
. By increasing the threshold voltage V
T
, a smaller subthreshold leakage current flows for a given gate-to-source voltage. The threshold voltage V
T
of a MOS transistor can be increased by increasing the magnitude of the voltage applied to the substrate of the transistor, which is known as the back-bias voltage and is typically designated V
bb
. The back-bias voltage V
bb
is applied to the substrate for proper operation of the MOS transistor as known in the art. Thus, the subthreshold leakage current of the MOS transistor can be decreased by a corresponding increase in the back-bias voltage V
bb
. When the threshold voltage V
T
is increased, however, the switching time of the MOS transistor increases accordingly because an input voltage coupled to the gate of the MOS transistor must now reach the higher threshold voltage V
T
before the transistor turns ON. In many integrated circuits, such as microprocessors, the threshold voltages V
T
must be maintained relatively low to decrease the switching time of the transistors. Thus, although the threshold voltage V
T
can be increased to lower the subthreshold leakage current of the transistor, in many applications the required performance of the integrated circuit will not allow such an increase in the threshold voltage V
T
.
There is a need for decreasing the subthreshold leakage current of MOS transistors forming an integrated circuit while at the same time allowing for high speed operation of such transistors.
SUMMARY OF THE INVENTION
An integrated circuit includes a substrate pump circuit developing an internal back-bias voltage on an output. An external terminal is adapted to receive an external back-bias voltage. A semiconductor substrate is coupled to the external terminal and to the output of the substrate pump circuit. The semiconductor substrate includes at least one transistor formed in the semiconductor substrate. The at least one transistor has a first threshold voltage when the internal back-bias voltage is applied to the semiconductor substrate, and a second threshold voltage greater than the first threshold voltage when the external back-bias voltage is received on the external terminal.
REFERENCES:
patent: 4473758 (1984-09-01), Huntington
patent: 4556804 (1985-12-01), Dewitt
patent: 4686388 (1987-08-01), Hafner
patent: 4961007 (1990-10-01), Kumanoya et al.
patent: 5448198 (1995-09-01), Toyoshima et al.
patent: 5461338 (1995-10-01), Hirayama et al.
patent: 5528538 (1996-06-01), Sakuta et al.
patent: 5604707 (1997-02-01), Kuge et al.
patent: 5959444 (1999-09-01), Casper
patent: 6026033 (2000-02-01), Casper
patent: 0 714 099 (1994-11-01), None
Cunningham Terry D.
Micro)n Technology, Inc.
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