Telecommunications – Transmitter and receiver at same station – With transmitter-receiver switching or interaction prevention
Reexamination Certificate
2001-07-11
2002-12-17
To, Doris H. (Department: 2682)
Telecommunications
Transmitter and receiver at same station
With transmitter-receiver switching or interaction prevention
C455S073000, C333S103000, C333S262000
Reexamination Certificate
active
06496684
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to a single pole single throw (SPST) switch, a single pole double throw (SPDT) switch, and a communication apparatus using the SPDT switch and, more particularly, to an SPST switch, an SPDT switch, as an antenna switch of a mobile communication apparatus and a communication apparatus using these switches.
2. Description of the Related Art
With a recent tendency to reduce the power consumption of mobile communication apparatuses, reductions in transmission loss and power consumption are required for an antenna switch.
FIG. 11
shows a circuit diagram of an SPST switch having a basic configuration which is disclosed in Japanese Unexamined Patent Publication No. 9-191268 as a conventional SPST (Single Pole Single Throw) switch (switch for connecting and disconnecting two terminals to each other). In
FIG. 11
, an SPST switch
1
includes a first terminal
2
, a second terminal
3
, a diode D
1
connected between the first terminal
2
and the second terminal
3
, an induction element L
1
and a capacitor element C
1
which are connected in series with each other and are connected in parallel with the diode D
1
, and a capacitor element C
2
connected in parallel with the diode D
1
.
In the SPST switch
1
arranged as described above, when a current flows in the diode D
1
, the diode D
1
is equivalent to a resistor having a small resistance (ON resistance), the first terminal
2
and the second terminal
3
are almost directly connected to each other, and the SPST switch
1
is turned on. At this time, the induction element L
1
or the capacitor elements C
1
and C
2
do not adversely affect a signal passing through the SPST switch
1
. In contrast, when no current flows in the diode D
1
, the diode D
1
is equivalent to a capacitor element having a small capacitance (OFF capacitance). However, in this case, the diode D
1
may resonate at a signal frequency which is a function of the OFF capacitance in parallel with the induction element L
1
and the capacitor elements C
1
and C
2
. An impedance between the first terminal
2
and the second terminal
3
becomes almost infinite, and the SPST switch
1
is turned off. In this manner, by controlling whether a current flows in the diode D
1
or not, the switch
1
exhibits the characteristics of an SPST switch.
FIG. 12
shows a circuit diagram of an SPST switch having a basic configuration which is disclosed as another conventional SPST switch in Japanese Unexamined Patent Publication No. 9-191268. The same reference numerals as in
FIG. 11
denote the same parts or similar parts in
FIG. 12
, and a detailed description thereof will be omitted. In
FIG. 12
, an SPST switch
4
is arranged such that a first terminal
2
and a second terminal
3
are connected to each other in series through a diode D
2
and an induction element L
2
, and a capacitor element C
3
is connected in parallel to the diode D
2
and the induction element L
2
.
In the SPST switch
4
arranged as described above, when a current flows in the diode D
2
, the diode D
2
can be almost neglected because the diode D
2
is equivalent to a resistor having a small resistance (ON resistance). The induction element L
2
and the capacitor element C
3
are connected in parallel with each other between the first terminal
2
and the second terminal
3
. When the values of the induction element L
2
and the capacitor element C
3
are set such that the induction element L
2
and the capacitor element C
3
resonate at a signal frequency, an impedance between the first terminal
2
and the second terminal
3
becomes almost infinite, and the SPST switch
4
is turned off. In contrast, when no current flows in the diode D
2
, the diode D
2
is equivalent to a capacitor element having a small capacitance (OFF capacitance) and the impedance of the path through the diode D
2
and the induction element L
2
between the first terminal
2
and the second terminal
3
is high. However, when the capacitance of the capacitor element C
3
is set to be a relatively large value, the impedance of the path through the capacitor element C
3
is low, the first terminal
2
and the second terminal
3
are almost directly connected to each other, and the SPST switch
4
is turned on. In this manner, the switch
4
exhibits the characteristics of an SPST switch by controlling whether a current flows in the diode D
2
or not. Note that the SPST switch
4
operates in reverse to the SPST switch
1
shown in
FIG. 11
by controlling whether a current flows in the diode or not.
FIG. 13
shows a circuit diagram of an SPST switch having a basic configuration which is disclosed as still another conventional SPST switch in Japanese Unexamined Patent Publication No. 7-303001. The same reference numerals as in
FIG. 11
denote the same parts or similar parts in
FIG. 13
, and a detailed description thereof will be omitted. In
FIG. 13
, an SPST switch
5
is arranged such that an induction element L
3
is connected to a first terminal
2
and a second terminal
3
, and a drain and a source of a FET Q
1
are connected to both terminals of the induction element L
3
, respectively. In this case, the gate of the FET Q
1
is connected to a control terminal
6
. In
FIG. 13
, with respect to the terminals of the FET Q
1
, a symbol D is added to only the drain, while symbols at the source and the gate are omitted.
In the SPST switch
5
arranged as described above, when the FET Q
1
is in an ON state, the source-drain portion of the FET Q
1
is equivalent to a resistor having a small resistance (ON resistance). For this reason, the first terminal
2
and the second terminal
3
are almost directly connected to each other through the FET Q
1
, and the SPST switch
5
is turned on. In contrast, when the FET Q
1
is in an OFF state, the source-drain portion of the FET Q
1
is equivalent to a capacitor element having a small capacitance (OFF capacitance). In this case, when only the FET Q
1
is connected between the first terminal
2
and the second terminal
3
, the OFF capacitance of the FET Q
1
operates to decrease the impedance between the first terminal
2
and the second terminal
3
. However, when the induction element L
3
is connected, it may resonate in parallel with the OFF capacitance of the FET Q
1
at a signal frequency, the impedance between the first terminal
2
and the second terminal
3
can be made almost infinite, and the SPST switch
5
is turned off. In this manner, when the FET Q
1
is turned on or off, the switch
5
exhibits the characteristics of an SPST switch.
When two SPST switches described above are combined with each other, the combination can also be operated as an SPDT (Single Pole Double Throw) switch (switch having three terminals in which one (common) terminal may be connected to either one of the two remaining terminals).
However, in the SPST switch
1
shown in
FIG. 11
, since the first terminal
2
and the second terminal
3
are connected to each other through the diode D
1
when the SPST switch
1
is in an ON state, a transmission loss, although it is small, is disadvantageously generated due to the ON resistance of the diode D
1
. In the SPST switch
4
shown in
FIG. 12
, since the first terminal
2
and the second terminal
3
are connected to each other through the capacitor element C
3
when the SPST switch
4
is in an ON state, a transmission loss is disadvantageously generated due to the impedance of the capacitor element C
3
. In any one of the SPST switches
1
and
4
, a direct current must continuously flow in the switches
1
or
4
to turn the diode D
1
or D
2
on, and a relatively large power consumption is disadvantageously required.
Also in the SPST switch
5
shown in
FIG. 13
, since the first terminal
2
and the second terminal
3
are connected to each other through the FET Q
1
when the SPST switch
5
is in an ON state, a transmission loss is disadvantageously generated due to the ON resistance of the FET Q
1
.
As in an SPDT switch, using the SPST switche
Nakao Motoyasu
Sasabata Akihiro
Tanaka Hiroaki
Ostrolenk Faber Gerb & Soffen, LLP
To Doris H.
LandOfFree
SPST switch, SPDT switch, and communication apparatus using... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with SPST switch, SPDT switch, and communication apparatus using..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and SPST switch, SPDT switch, and communication apparatus using... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2984977