Delta sigma digital-to-analog converter

Details Delta sigma digital-to-analog converter Delta sigma digital-to-analog converter

2000-06-06

2002-02-05

Lam, Tuan T. (Department: 2816)

Coded data generation or conversion

Analog to or from digital conversion

Differential encoder and/or decoder

C341S144000

Reexamination Certificate

active

06344812

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a delta sigma (modulation) digital-to-analog converter (DAC) for digital audio equipment having a low distortion factor and a high S/N (signal to noise) ratio, and more particularly to a delta sigma digital-to-analog converter having a quantizer connected to a local digital-to-analog converter and having three or more quantizing levels.
2. Description of the Related Art
The delta sigma (modulation) DAC is widely used in audio equipment. The performance of a digital-to-analog converter in audio equipment is principally represented by factors such as a distortion factor (a ratio of a harmonic component to a signal) and a signal to noise (SIN) ratio. The performance of digital-to-analog converters in related art largely depends on absolute and relative variations in characteristics of components such as resistors and capacitors rather than circuit types, which variations are difficult to reduce in newer more precise components. Compared with this, in the delta sigma converter for which quantizing levels ranging only from two (1 bit) to several are required, the variations among components do not become a problem as in the related art converter. In recent years, however, higher performance has been required for digital-to-analog converters used in audio equipment so as to comply with the new 24 bit format of Digital Video Disc (DVD), as opposed to prior 16 bit format of Compact Disc (CD).
In order to improve the distortion factor and the S/N ratio, it is theoretically possible to increase any of the following: (1) the order of the delta sigma modulator; (2) the sampling frequency; or (3) the number of quantized levels (i.e., the number of bits) (See, e.g., “An oversampling A-D/D-A conversion technique (2)”, Nikkei Electronics Aug. 8, 1988, No. 453, pp. 211-221).
An excessive increase in the order of the delta sigma modulator, however, is unsuitable for maintaining the stability of the feedback system called the “noise shaper.” A noise shaper arithmetic unit is a one which converts a multi-bit digital signal, input by oversampling, to a digital signal with lower bits than those of the multi-bit digital signal by noise shaper operation and outputs it from a quantizer. Referring to
FIG. 1
, a third-order noise shaper arithmetic unit is shown which comprises multipliers Y
1
and Y
2
, delay circuits Y
3
, Y
4
and Y
5
, and adders Y
6
and Y
7
. The delay circuits Y
3
, Y
4
and Y
5
, which each provide a delay by one sampling period, are connected in series in numerical order. At adder Y
6
, an output from the delay circuit Y
5
and outputs from the multipliers Y
1
and Y
2
are added to the input multi-bit digital signal (e.g., a 22 bit digital signal). At the multipliers Y
1
and Y
2
, outputs from the delay circuits Y
3
and Y
4
are multiplied by coefficients 3 and −3, respectively. The result of the addition output from adder Y
6
is input to quantizer
1
. The output of quantizer
1
is branched and subtracted from the input thereto at adder Y
7
to be an input to delay circuit Y
3
. In
FIG. 1
, an arithmetic unit is shown in which a 22 bit digital signal is input for conversion to a 4 bit digital signal with 11 levels.
With respect to increasing the sampling frequency, i.e., increasing the operating frequency of the noise shaper arithmetic unit, this requires that the frequency of the system clock in the associated audio equipment be increased. This results in an increase in the cost of the audio equipment and in its power consumption, and also may cause interference noise in the analog audio system. As a result, the benefits of an increase in sampling frequency is limited to a certain extent.
In view of the foregoing, the best way to provide a delta sigma digital-to-analog converter with a reduced distortion factor and an improved S/N ratio is to adequately set the order of the delta sigma modulator and the sampling frequency therefor to increase the number of quantized levels. In order to adequately set the order of the delta sigma modulator and the sampling frequency therefor for increasing the number of quantized levels, a local digital-to-analog converter may be added which carries out a digital-to-analog conversion of the output of the built-in quantizer.
The resolution of the local digital-to-analog converter in the delta sigma modulation system is a minimum of 2 levels and at most several tens levels. Conventionally, Pulse Width Modulation (PWM) digital-to-analog converters or Dynamic Element Matching (DEM) digital-to-analog converters have been used in systems having three or more levels.
The PWM converter offers the advantage of higher precision because a plurality of levels are presented in a sampling period by using a clock frequency several times the sampling frequency, which clock frequency is provided by a highly precise quartz oscillator which determines the precision of conversion. However, the need to use an expensive high precision clock in PWM operation is a disadvantage of the PWM converter.
As for the DEM converter, a digital-to-analog converter is used with a plurality of converting elements for carrying out respective conversions at the same time. In this case, the DEM converter provides a delta sigma modulation in which the sampling frequency is set comparably high.
The DEM converter is provided with a plurality of analog elements such as resistors and capacitors, so that, when the elements are provided are included in an integrated circuit, the precision of the DEM converter depends on relative variations among elements which occur in the semiconductor production process for the integrated circuit. In order to reduce the influence of these variations on the precision of the converter, the DEM converter is operated so that all of the elements are configured so that they are equally used within a certain period of time according to a specified procedure. This method allows realization of better conversion precision than would result when simply relying upon the precision of the elements caused by the relative variations in the semiconductor production process.
A specific example of a prior art delta sigma digital-to-analog converter is shown in FIG.
2
. Hereinafter, the multi-level digital-to-analog converter is referred as the multi-level DAC. In
FIG. 2
, the highest level of the multi-level DAC is shown as level 11 for ease of the explanation. In addition, twelve 1 bit local DACs are provided (LDAC
1
to LDAC
12
). For ease of explanation, hereinafter the local DACs LDAC
1
to IDAC
12
are referred to as simply IDAC
1
to LDAC
12
. In operation, there will be no case in which all of the IDAC
1
to LDAC
12
are turned on, that is, unit amounts are given to all of them. The digital-to-analog converter shown in
FIG. 2
comprises a thermometer code converter
2
which outputs a thermometer code corresponding to the number of output levels from quantizer
1
(which is shown in detail in FIG.
1
), a barrel shifter X
3
which shifts in rotation a bit arrangement of the thermometer code very sampling period, IDAC
1
to LDAC
12
which are equally weighted to each other (i.e., provided with resistors with resistance values equal to each other), and an analog adder X
4
. The thermometer code converter
2
produces a thermometer code with the number of bits corresponding to the number of the output levels from quantizer
1
. Along with this, barrel shifter X
3
shifts in rotation the bit arrangement of the thermometer code to selectively supply currents (unit amounts) to the LDAC
1
to LDAC
12
. The unit amount supplied to each of the local DAC's is added to others to generate an analog output corresponding to the output levels of quantizer
1
.
However, a conventional DEM converter shifts the thermometer code every sampling frequency period to supply in order the unit amount equally to the N local DACs and therefore has the following problem. The mode of rotation of the unit amount in the local DACs changes depending on the output data of quantizer
1
conver

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