Register file access

Details Register file access Register file access

1999-04-29

2002-02-05

Pan, Daniel H. (Department: 2783)

Electrical computers and digital processing systems: processing

Instruction decoding

Predecoding of instruction component

C712S220000, C714S034000, C711S125000, C711S123000, C713S322000, C713S502000

Reexamination Certificate

active

06345354

ABSTRACT:

BACKGROUND OF THE INVENTION
This invention relates generally to the field of microprocessors. More particularly, it relates to the area of accessing a register file within a microprocessor.
In the area of microprocessors, power is typically an important concern. This is especially true in devices that operate in a standalone manner, such as in many consumer devices. Such is the case because these devices must often operate from small power supplies. As the number of features incorporated into a chip increases, it can become even more important to conserve power whenever possible. Other benefits to be gained by reducing the power required by a processor include reducing the size and weight of a power supply as well as reducing the heat generated by the processor.
An area that often conflicts with power consumption in the field of microprocessors is the efficient or fast operation of the processor. The ability to operate the processor in a fast manner often leads to greater performance of the processor. Hence, it is usually desirable to operate a processor at its greatest speed possible. One technique to generate fast operation is the speculative enablement of the output of a register. This type of operation allows the register information to be ready when it might be required by an execution unit in the processor. However, it will not always be required. For example, in the case where speculative instructions are issued, a register associated with the instruction is also speculatively enabled such that a read access of the register file can occur. Thus, when the instruction is not required, power has been wasted in enabling the output lines of the register. (A speculative instruction might be cancelled, for example, when it is learned that a branch misprediction occurred.) Similarly, register information in the past has been unnecessary when operand information is bypassed due to its invalid status. In some processors this could happen in perhaps 50% of all instructions. This is due to the fact that compilers sequence program steps such that common operands are used by successive instructions. Therefore, operand information at an execution unit is sometimes more accurate than the operand information in the register—hence a bypass of the register is issued and the operand at the execution unit is used in place of the operand stored in the register. Once again allowing a register file access to occur in such a situation is wasteful. Nevertheless, such enablement has been used in the past when attempting to run the processor at a fast rate. Hence, in the past there has been a tradeoff between speed and power consumption for microprocessors.
As the foregoing illustrates, there is a need for a microprocessor that permits relatively fast operation (such as through speculative operations) while conserving power. More particularly, there is a need for a manner of accessing a register within a register file that facilitates fast operation while also conserving power.
SUMMARY OF THE INVENTION
The present invention provides a method, apparatus, and article of manufacture that facilitate conservation of power while allowing for fast system (e.g., microprocessor) operation.
One embodiment of the invention provides a method and apparatus in which a register file access in a microprocessor can be enhanced. The invention provides a register which is adapted to store information, provides a clock signal that defines a first phase and a second phase, decodes register information during the first phase that specifies the register in which the information is stored, and enables at least one register bit line of the register during the second phase of the clock signal.
In other embodiments of the invention bypass control logic and/or instruction dispatch control logic control whether the output from the register should be enabled.
These and other embodiments of the invention can be implemented in a variety of formats. This could include at least an actual integrated circuit, a core for insertion within an application specific integrated circuit (ASIC), as well as computer code that can wholly or partly describe (for such purposes as modeling or semiconductor manufacturing), the apparatus and/or method.
In accordance with the present invention, speculative instructions may be issued and the benefits from such instructions derived while reducing or eliminating the consequence of wasted power on an unnecessarily enabled register (such as, for example, when the register information is bypassed, a dispatch stall occurs, or some other reason removes the need for the register information).
Other and further advantages and features of the invention will be apparent to those skilled in the art from a consideration of this description taken in conjunction with the accompanying drawings, wherein certain methods of practicing the invention are illustrated. However, it is to be understood that the invention is not limited to the details disclosed herein but includes all such variations and modifications as fall within the spirit of the invention and the scope of the appended claims.


REFERENCES:
patent: 5394450 (1995-02-01), Pasternak
patent: 5398330 (1995-03-01), Jonhson
patent: 5544342 (1996-08-01), Dean
patent: 5623700 (1997-04-01), Parks et al.
patent: 5710578 (1998-01-01), Beauregard et al.

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