Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Particular stable state circuit
Reexamination Certificate
2001-12-12
2002-12-31
Callahan, Timothy P. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Particular stable state circuit
C327S203000, C327S208000, C327S211000
Reexamination Certificate
active
06501315
ABSTRACT:
FIELD OF THE INVENTION
The invention relates to the sequential storage circuits commonly referred to as “flip-flops”. More particularly, the invention relates to a high-speed flip-flop that operates at very low voltage levels and can offer set and/or reset capability.
BACKGROUND OF THE INVENTION
Flip-flops are sequential circuits storing either a “high” value (power high, or logic one) or a “low” value (power low, or logic zero). A flip-flop has a next value that depends on the values of one or more input signals. Conventionally, a flip-flop has data, clock, set, and/or reset input signals.
A D (data) input signal is typically clocked into the flip-flop on receipt of a given clock edge, and appears at the flip-flop output on the opposite clock edge. S (set) and R (reset) input signals are generally unclocked, meaning that when the set or reset signal becomes active (e.g., goes high), the stored value changes immediately, without waiting for the arrival of a clock edge. An active set signal forces the stored value (conventionally designated Q) high, no matter what value was previously stored. An active reset signal forces the stored value Q low, no matter what value was previously stored. In set/reset flip-flops (i.e., flip-flops having both set and reset input signals) the set and reset signals are typically restricted such that at most one of them can be active at any given time.
Flip-flops are often designed using two latches separated by passgates.
FIG. 1
shows such a flip-flop, comprising a first latch including cross-coupled inverters
101
and
102
, a second latch including cross-coupled inverters
103
and
104
, and passgates
106
,
107
. The clock signal C is inverted by inverter
105
to provide inverted clock signal CB. On the falling edge of the clock signal C (or whenever signal C is low), signal CB goes high, and the data signal D passes through passgate
106
to node A, and hence into the first latch. (In the present specification, the same reference characters are used to refer to terminals, signal lines, and their corresponding signals.) The data value is inverted by inverter
101
, and appears at node B. On the next rising edge of clock signal C, the inverted data from node B passes through passgate
107
to node QB (the inverted output signal), and hence into the second latch. The data is again inverted by inverter
103
, and appears on the output node Q.
For the flip-flop to function properly, it must be possible to write a high value to each of nodes A and QB, and ensure that the new value overcomes a low value previously stored on the node. The new high value must pass through either passgate
106
or passgate
107
, and overcome the zero value being provided by inverter
102
or inverter
104
, respectively. When passing through an N-channel transistor, a high voltage value is reduced by the threshold voltage of the transistor. Therefore, if an N-channel transistor is used to implement the passgate, as shown in
FIG. 1
, inverters
102
and
104
are necessarily designed to be weak, and correspondingly slow. (Writing low values is not an issue, because there is no voltage degradation of a low signal through an N-channel transistor.)
At very low voltages, the high voltage value (VDD) approaches the threshold voltage of an N-channel transistor, which is generally about 0.7 volts. It is not practical to reduce this threshold voltage, because transistors with a lower threshold voltage would become unacceptably sensitive to noise. Therefore, at very low voltages, the high value passed through the passgate is not sufficient to overcome even a weak inverter (e.g., inverter
102
in FIG.
1
), and therefore may not be high enough to trip inverter
101
. The same limitation applies to passgate
107
and inverters
104
,
103
. One known solution is to implement the passgates using CMOS passgates (i.e., paired N-channel and P-channel transistors), as shown in FIG.
2
.
FIG. 2A
shows a well-known flip-flop similar to that of FIG.
1
. The N-channel transistors forming passgates
106
,
107
in
FIG. 1
are replaced by CMOS passgates
206
,
207
, respectively. The P-channel gate terminals are driven by the inverse of the signals used to drive the N-channel gate terminals. A high value on data input D or node B is not reduced as it passes through the P-channel transistor. Therefore, the substitution of the CMOS passgates for the simple N-channel transistors ensures that new high values will be successfully latched, even at low voltages. (Of course, the high voltage level must be higher than the threshold voltage of the N-channel transistor, or no circuit containing N-channel transistors will function properly.)
A disadvantage of using CMOS passgates in flip-flops is that P-channel transistors are relatively slow compared to similarly-sized N-channel transistors. Because flip-flops are ubiquitous in nearly all integrated circuits, minimum sized gates are usually used to implement flip-flops. Passing a high logic level through a minimum sized P-channel transistor introduces a delay that can become significant.
Therefore, the flip-flop of
FIG. 2A
also includes another modification, which improves the operating speed of the flip-flop. CMOS passgates
208
and
209
are inserted into the latch feedback loops after inverters
202
and
204
, respectively. When clock signal C goes low and inverted clock signal CB goes high, CMOS passgate
206
is turned on. In the flip-flop of
FIG. 1
, an incoming high data signal must then overcome a low value on node A driven by inverter
102
. In the flip-flop of
FIG. 2A
, however, passgate
208
is turned off (because clock signal C is low), and there is no driving inverter to be overcome by the new high value. Similarly, when clock signal C goes high and inverted clock signal CB goes low, passgate
209
is turned off, and a high value on node B passes onto node QB unopposed by inverter
204
. Thus, the latches in
FIG. 2A
change state more rapidly than the corresponding latches in FIG.
1
.
FIG. 2B
shows another prior art flip-flop similar to that of FIG.
2
A. In the flip-flop of
FIG. 2A
, passgates (
208
,
209
) are inserted between the outputs terminals of the feedback inverters (
202
,
204
) in the latches and the nodes (A, QB) by which data is passed to the latches. These passgates provide a means for electrically isolating the feedback inverters from the-nodes when new data is provided to the latches. However, writing a low value to a latch is generally not a problem, even at low voltages. The problems are encountered only when writing a high value to the latch while overcoming a low value provided by the feedback inverter. Therefore, when writing any new value to the latch, it is only necessary to prevent the feedback inverter from driving a low value.
In the flip-flop of
FIG. 2B
, P-channel transistor
211
and N-channel transistor
213
form an inverter driven by node B (corresponding to inverter
202
in FIG.
2
A). Inserted into the pull-down path of the inverter is an N-channel transistor
212
gated by the clock signal C. Thus, when clock signal C goes low, the new data (e.g., a high value) is written from data input terminal D to node A. Because clock signal C is low, no low signal is provided through N-channel transistor
213
. Therefore, the new high value on node A is unopposed.
Similarly, P-channel transistor
221
and N-channel transistor
223
form an inverter driven by node Q (corresponding to inverter
204
in FIG.
2
A). Inserted into the pull-down path of the inverter is an N-channel transistor
222
gated by inverted clock signal CB. Thus, when clock signal C goes high, the new data (e.g., a high value) is written from node B to node QB. Because inverted clock signal CB is low, no low signal is provided through N-channel transistor
223
. Therefore, the new high value on node QB is unopposed.
It is possible to include feedback passgates
208
and
209
(
FIG. 2A
) or N-channel transistors
212
and
222
(
FIG. 2B
) while using N-channel transistors
106
and
107
(
FIG. 1
) instead of CMOS pa
Callahan Timothy P.
Cartier Lois D.
Luu An T.
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