Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Of specified configuration
Reexamination Certificate
1999-09-08
2002-12-24
Fahmy, Wael (Department: 2823)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Of specified configuration
C438S638000
Reexamination Certificate
active
06498399
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention pertains to the formation of microelectronic devices such as integrated circuit devices. More particularly, the invention relates to the formation of vias and trenches, or interconnect metallization and wiring lines using multiple low dielectric constant intermetal dielectrics.
2. Description of the Related Art
In the production of microelectronic devices, the levels of multilevel wiring structures have interconnecting regions for interconnecting one or more devices within overall integrated circuits. In forming such devices, it is conventional to form lower level wiring lines, then an interlevel dielectric layer and then to form upper level wiring lines. One or more metal filled vias are typically formed in the interlevel dielectric to connect the upper and lower level wiring lines.
One conventional method for forming a two level wiring structure is to first form a two level interconnect structure over a substrate. The surface of a substrate may be the surface of a silicon device structure or the surface of substrate may be an insulating layer. An oxide layer is typically deposited over the substrate by chemical vapor deposition. The first, level interconnect structures are defined by a conventional photolithography process which forms openings through the oxide layer where the first level interconnects will be formed. Generally, the openings expose portions of conductors in the substrate to which interconnects are formed. The openings are filled with a metal interconnect to form the interconnect and form a metal plug. Then a layer of metal such as aluminum is deposited over the surface of the oxide layer and over the metal plug to a thickness appropriate for second level wiring lines. The metal layer is then patterned into the second level wiring lines. The second level wiring lines are defined in a conventional photolithography process by providing a layer of photoresist over the metal layer, exposing the photoresist through a mask and removing portions of the exposed photoresist layer to form a photoresist etch mask. The portions of the metal layer exposed by openings in the photoresist mask are then removed by etching and the photoresist mask is removed by ashing. After the two level interconnect structure is formed,it is necessary to provide an intermetal dielectric (IMD) layer between the second level wiring lines and covering the second level wiring lines to accommodate further processing of the integrated circuit device. In the past, the intermetal dielectric layer might consist of one or more layers of oxide deposited by plasma enhanced chemical vapor deposition or other processes.
Prior art integrated circuits produced by single or dual damascene processes with Cu interconnects and low dielectric-constant (k) intermetal dielectrics have used only one kind of low-k dielectric, either inorganic, organic or a hybrid of these two kinds. This conventional approach of using the same kind of low-k dielectric for both metal-level and via-level IMD's has limited process integration and implementation options. As a result, additional processing steps and added cost are required. This conventional approach of using the same kind of low-k dielectric for both metal-level and via-level IMD's also requires an etchstop, usually silicon nitride, between the metal-level and via-level inter-metal dielectrics, IMD's. The use of silicon nitride, which has a high dielectric constant of 7, seriously degrades the speed performance of integrated circuits. It is desirable whenever possible to reduce the number of processing steps required to form a device because reducing the number of processing steps shortens the time required to produce the device and because eliminating processing steps improves yields and so reduces costs.
The present invention uses two dissimilar low-k dielectrics for the intermetal dielectrics of Cu-based dual damascene backends of integrated circuits. The use of both organic and inorganic low-k dielectrics offers several advantages due to the significantly different plasma etch characteristics of these two kinds of dielectrics. One dielectric serves as an etchstop in etching the other dielectric. No additional oxide or nitride etchstop layer is required. High performance is achieved due to the lower parasitic capacitance resulting from the use of low-k dielectrics. This invention takes the advantage that inorganic and organic dielectric are significantly in their plasma etch characteristics. Either can be made the etchstop in plasma etching the other one. It is apparent that in the conventional approach having the same kind of dielectric for both via-level and metal-level IMD's, that additional thin films need be deposited to establish the existence of etchstop in the conventional architecture. In oxygen-based plasmas, organic dielectrics etch tremendously faster than inorganic dielectrics. Inversely, in carbon fluoride based plasmas, inorganic dielectrics etch significantly faster than organic dielectrics.
SUMMARY OF THE INVENTION
The invention provides a microelectronic device which comprises
(a) a substrate;
(b) a layer of a first dielectric material positioned on the substrate;
(c) a layer of a second dielectric material positioned on the first dielectric layer; wherein the first dielectric material and the second dielectric material have substantially different etch resistance properties;
(d) an additional layer of the first dielectric material positioned on the second dielectric material,
(e) at least one via extending through the first dielectric material layer and the second dielectric material layer, and at least one trench through the additional layer of the first dielectric material extending to at least one via;
(f) a lining of a barrier metal on inside walls and a floor of the trench and on inside walls and a floor of the via;
(g) a fill metal filling the trench and via in contact with the lining of the barrier metal.
The invention also provides a process for producing a microelectronic device which comprises:
(a) forming a first dielectric layer on a substrate;
(b) forming a second dielectric layer on the first dielectric layer;
(c) forming an additional first dielectric layer on the second dielectric layer;
(d) depositing a layer of a photoresist on the additional first dielectric layer and imagewise removing a portion of the photoresist corresponding to at least one via for the first dielectric layer;
(e) sequentially removing the portions of the additional first dielectric layer, the second dielectric layer and the first dielectric layer under the removed portion of the photoresist thus forming at least one via through the first dielectric layer; and then removing the balance of the photoresist layer;
(f) depositing an additional layer of a photoresist on the additional first dielectric layer and imagewise removing a portion of the additional photoresist corresponding to at least one trench for the additional first dielectric layer;
(g) removing the portion of the additional first dielectric layer under the removed portion of the additional photoresist layer thus forming at least one trench through the additional first dielectric layer;
(h) optionally removing the portion of the second dielectric layer under the removed portion of the additional photoresist layer;
(i) removing the balance of the additional photoresist layer;
(j) lining a barrier metal on inside walls and a floor of the trench and on inside walls and a floor of the via;
(k) filling the trench and via with a fill metal in contact with the lining of the barrier metal.
The invention further provides a process for producing a microelectronic device which comprises:
(a) forming a first dielectric layer on a substrate;
(b) depositing a layer of a photoresist on the first dielectric layer and imagewise removing a portion of the photoresist corresponding to at least one via for the first dielectric layer;
(c) removing the portion of the first dielectric layer under the removed portion of the photoresist t
Chung Henry
Lin James
Allied-Signal Inc.
Coleman William David
Fahmy Wael
Roberts & Mercanti LLP
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