Semiconductor device manufacturing: process – Chemical etching – Combined with the removal of material by nonchemical means
Reexamination Certificate
2000-02-28
2002-12-24
Powell, William A. (Department: 1765)
Semiconductor device manufacturing: process
Chemical etching
Combined with the removal of material by nonchemical means
C156S345420, C216S038000, C216S088000, C216S089000, C216S091000, C438S692000, C438S693000, C438S745000
Reexamination Certificate
active
06498101
ABSTRACT:
TECHNICAL FIELD
The present invention relates to planarizing pads and methods for making and using planarizing pads in mechanical and chemical-mechanical planarization of semiconductor wafers, field emission displays, and other microelectronic device substrate assemblies.
BACKGROUND OF THE INVENTION
Mechanical and chemical-mechanical polishing processes (collectively “CMP”) remove material from the surface of microelectronic substrates in the production of microelectronic devices and other products.
FIG. 1
schematically illustrates a rotary CMP machine
10
with a platen
20
, a wafer carrier
30
, and a planarizing pad
40
. The CMP machine
10
may also have an under-pad
25
between an upper surface
22
of the platen
20
and a lower surface of the planarizing pad
40
. A drive assembly
26
rotates the platen
20
(indicated by arrow F), or it reciprocates the platen
20
back and forth (indicated by arrow G). Since the planarizing pad
40
is attached to the under-pad
25
, the planarizing pad
40
moves with the platen
20
during planarization.
The wafer carrier
30
has a lower surface
32
to which a wafer
12
may be attached, or the wafer
12
may be attached to a resilient pad
34
under the lower surface
32
. The wafer carrier
30
may be a weighted, free-floating wafer carrier, or an actuator assembly
36
may be attached to the wafer carrier to impart axial and/or rotational motion to the wafer
12
(indicated by arrows I and J, respectively).
The planarizing pad
40
and the planarizing solution
44
defame a planarizing medium that mechanically and/or chemically-mechanically removes material from the surface of the substrate
12
. The planarizing pad
40
can be a fixed-abrasive planarizing pad having abrasive particles fixedly bonded to a suspension material. In fixed-abrasive applications, the planarizing solution is generally a “clean solution” without abrasive particles. In other applications, the planarizing pad
40
can be a non-abrasive pad composed of a polymeric material (e.g., polyurethane, polycarbonate or polyester), felt, resin or other suitable materials. The planarizing solutions
44
used with the non-abrasive planarizing pads are typically CMP slurries with abrasive particles and chemicals.
To planarize the wafer
12
with the CMP machine
10
, the wafer carrier
30
presses the wafer
12
face-downward against the planarizing pad
40
. More specifically, the wafer carrier
30
generally presses the wafer
12
against the planarizing liquid
44
on a planarizing surface
42
of the planarizing pad
40
, and the platen
20
and/or the wafer carrier
30
moves to rub the wafer
12
against the planarizing surface
42
. As the wafer
12
rubs against the planarizing surface
42
, the planarizing medium removes material from the face of the wafer
12
.
CMP processes should consistently and accurately produce a uniformly planar surface on the substrate to enable precise fabrication of circuits and photo-patterns. During the fabrication of transistors, contacts, interconnects and other features, many substrates develop large “step heights” that create highly topographic surfaces. Such topographical surfaces can impair the accuracy of subsequent photolithographic procedures and other processes that are necessary for forming sub-micron features. For example, it is difficult to accurately focus photo patterns to within tolerances approaching 0.1 micron on topographic surfaces because sub-micron photolithographic equipment generally has a very limited depth of field. Thus, CMP processes are often used to transform a topographical surface into a highly uniform, planar surface at various stages of manufacturing microelectronic devices.
One problem with many CMP processes is that the surface of the wafer may not be uniformly planar because the rate at which material is removed from the wafer (the “polishing rate”) may vary from one area of the wafer to another. The characteristics of the planarizing pad generally influence the variance of the polishing rate globally across the substrate surface and also at a smaller scale across the individual dies (“chips”) on the substrate. For example, hard or incompressible planarizing pads quickly remove high points on the substrate to produce a good planarity across the individual dies, but hard pads generally produce large variances in the polishing rate in a band about 10 mm inward from the perimeter edge (“edge effects”). Hard pads may thus produce poor global planarity on a substrate. Soft or compressible planarizing pads, on the other hand, generally produce good global planarity because they mitigate edge effects, but soft pads may follow the topography between dies and periphery areas such that they produce “doming” over the individual dies. Soft pads accordingly produce poor planarity at a die level on a substrate. Therefore, neither hard nor soft pads produce good planarity at a global level without producing doming over the dies.
To resolve the problems associated with hard and soft planarizing pads, several conventional pads have a combination of soft and hard materials including a soft base layer and an inflexible, hard planarizing layer on the base layer. The planarizing layer contacts the surface of the substrate during a planarizing cycle and the base layer distributes differences in pressure between the pad and the substrate. Although such two-layer pads provide an improvement over single-layer pads, the hard planarizing layer still produces edge effects on the substrates in many applications. This drawback is expected to become even more prominent for CMP of twelve-inch wafers instead of eight-inch wafers.
SUMMARY OF THE INVENTION
The present invention relates to planarizing pads and methods for making or using planarizing pads to polish or planarize semiconductor wafers, field emission displays, or other microelectronic substrates and substrate assemblies. In one embodiment, the planarizing pad comprises a compressible body and a plurality of discrete contact elements. The compressible body can comprise a base having a backside facing a support surface of a table and a front side facing away from the support surface. The contact elements can comprise raised sections of a single layer or separate plates. The contact elements have a bottom surface attached to the front side of the base and a top surface facing away from the base. The compressible body has a first hardness and the contact elements have a second hardness greater than the first hardness, and/or the compressible body has a first compressibility and the contact elements have a second compressibility less than the first compressibility. The compressible body can be a compressible foam (e.g., foamed polyurethane), and the contact elements can be a hard, rigid material (e.g., polycarbonate, resin, polyester, or high density polyurethane). In operation, the contact elements can move independently from one another in a direction transverse to the substrate.
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Micro)n Technology, Inc.
Perkins Coie LLP
Powell William A.
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