Active solid-state devices (e.g. – transistors – solid-state diode – With means to control surface effects – Insulating coating
Reexamination Certificate
2001-02-06
2002-10-08
Flynn, Nathan J. (Department: 2826)
Active solid-state devices (e.g., transistors, solid-state diode
With means to control surface effects
Insulating coating
C257S634000, C257S636000, C257S637000, C257S638000
Reexamination Certificate
active
06462402
ABSTRACT:
TECHNICAL FIELD
The present invention relates to methods and apparatuses for endpointing a planarization process of a microelectronic substrate.
BACKGROUND OF THE INVENTION
Mechanical and chemical-mechanical planarization processes (collectively “CMP”) are used in the manufacturing of microelectronic devices for forming a flat surface on semiconductor wafers, field emission displays and many other microelectronic substrates.
FIG. 1
schematically illustrates a planarizing machine
10
with a platen or table
20
, a carrier assembly
30
above the platen
20
, a polishing pad
21
on the platen
20
, and a planarizing fluid
23
on the polishing pad
21
. The planarizing machine
10
may also have an under-pad
25
attached to an upper surface
22
of the platen
20
for supporting the polishing pad
21
. In many planarizing machines, a platen drive assembly
26
rotates (arrow A) and/or reciprocates (arrow B) the platen
20
to move the polishing pad
21
during planarization.
The carrier assembly
30
controls and protects a substrate
80
during planarization. The carrier assembly
30
typically has a substrate holder
32
with a pad
34
that holds the substrate
80
via suction. A carrier drive assembly
36
typically rotates (arrow C) and/or translates (arrow D) the substrate holder
32
. The substrate holder
32
, however, may be a weighted, free-floating disk (not shown) that slides over the polishing pad
21
.
The combination of the polishing pad
21
and the planarizing fluid
23
generally defines a planarizing medium
28
that mechanically and/or chemically mechanically removes material from the surface of the substrate
80
. The polishing pad
21
may be a conventional polishing pad composed of polymeric material (e.g., polyurethane) without abrasive particles, or it may be an abrasive polishing pad with abrasive particles fixedly bonded to a suspension material. In a typical application, the planarizing fluid
23
may be a CMP slurry with abrasive particles and chemicals for use with a conventional, nonabrasive polishing pad. In other applications, the planarizing fluid
23
may be a chemical solution without abrasive particles for use with an abrasive polishing pad.
To planarize the substrate
80
with the planarizing machine
10
, the carrier assembly
30
presses the substrate
80
against a planarizing surface
24
of the polishing pad
21
in the presence of the planarizing fluid
23
. The platen
20
and/or the substrate holder
32
then move relative to one another to translate the substrate
80
across the planarizing surface
24
. As a result, the abrasive particles and/or the chemicals in the planarizing medium
28
remove material from the surface of the substrate
80
.
CMP processes must consistently and accurately produce a uniform, planar surface on the substrate to enable precise fabrication of circuits and photopatterns. Prior to being planarized, many substrates have large “step heights” that create a highly topographic surface across the substrate. Yet, as the density of integrated circuits increases, it is necessary that the substrate have a planar surface at several processing stages because non-uniform substrate surfaces significantly increase the difficulty of forming sub-micron features or photopatterns to within a tolerance of approximately 0.1 &mgr;m. Thus, CMP processes must typically transform a highly topographical substrate surface into a highly uniform, planar substrate surface (e.g., a “blanket surface”).
In the competitive semiconductor industry, it is highly desirable to maximize the throughput of CMP processing by producing a blanket surface on a substrate as quickly as possible. The throughput of CMP processing is a function of several factors, one of which is the ability to accurately stop CMP processing at a desired endpoint. In a typical CMP process, the desired endpoint is reached when the surface of the substrate is a blanket surface and/or when enough material has been removed from the substrate to form discrete components on the substrate (e.g., shallow trench isolation areas, contacts, damascene lines, etc.). Accurately stopping CMP processing at a desired endpoint is important for maintaining a high throughput because the substrate may need to be re-polished if the substrate is “underplanarized.” Accurately stopping CMP processing at the desired endpoint is also important because too much material can be removed from the substrate, and thus, the substrate may be “over-polished.” For example, over-polishing can cause “dishing” in shallow-trench isolation structures, or over-polishing can completely destroy a section of the substrate. Thus, it is highly desirable to stop CMP processing at the desired endpoint.
In one conventional method of forming substrates with shallow-trench isolation structures, the substrate is etched to form shallow trenches between pads on which devices (such as transistors) are later formed. Each pad has a generally flat upper surface that forms initially sharp corners with the adjacent trenches to maximize the amount of surface area on the pad available for forming semiconductor devices. The pads generally include a pad oxide layer that is used as an etch stop for later processing, and the walls of the trenches are generally coated with a thermally-grown oxide layer.
One problem with the trench formation method discussed above is that the trench oxide layer may tend to “creep” between the pad and the pad oxide layer, rounding the edges of the pad and reducing the pad area available for forming devices. One approach to addressing this problem has been to apply a layer of nitride on top of the pad oxide to stiffen the pad oxide and reduce the tendency for the trench oxide layer to round the corners of the pads. The nitride layer can then be used to endpoint a subsequent planarization process and prevent planarization of the adjacent pad oxide layer. For example, the endpoint can be detected by sensing a change in friction between the substrate and the polishing medium when the polishing medium encounters the nitride layer. Detecting the endpoint by sensing such a change in friction is disclosed in U.S. Pat. No. 5,036,015.
One problem with the nitride layer is that it can be so hard and brittle that when it comes into contact with the planarizing medium the nitride fractures, creating chips or fragments. The nitride chips or fragments can become suspended in the planarizing liquid where they can scratch the surface of the substrate and/or otherwise damage the substrate. The damaged substrate must generally either be discarded or repaired, reducing the overall efficiency of the manufacturing operation.
Nitride has also been used outside the context of shallow-trench isolation structures in a process termed Local Oxidation of Silicon (LOCOS) to form active device regions on a silicon substrate. In one process, described in U.S. Pat. No. 5,358,892, a long “birds beak” oxidation region forms adjacent the active device region and can encroach into the active device region. The process can accordingly include disposing a nitride layer in the active device region to reduce encroachment by the bird's beak, and disposing a polysilicon layer between the nitride layer and the active device region to provide stress relief. The polysilicon and nitride layers are later etched away.
SUMMARY OF THE INVENTION
The present invention is directed toward methods and apparatuses for endpointing a planarizing process of a microelectronic substrate. In one aspect of the invention, the microelectronic substrate can include a semiconductor material having a first surface and a second surface opposite the first surface. The first surface can include a component region and at least one isolating region adjacent the component region. The isolating region and the component region can be located at different distances from the second surface of the semiconductor material, and the isolating region can include a generally sharp corner where it intersects the component region. The microelectronic substrate can further include a
Dickey Thomas L.
Dorsey & Whitney LLP
Flynn Nathan J.
Micro)n Technology, Inc.
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