Electrical computers and digital processing systems: processing – Processing architecture – Array processor
Reexamination Certificate
1999-06-15
2002-02-26
Pan, Daniel H. (Department: 2183)
Electrical computers and digital processing systems: processing
Processing architecture
Array processor
C712S014000, C712S017000, C712S018000, C712S030000, C712S244000, C711S210000, C711S206000, C709S248000, C709S249000
Reexamination Certificate
active
06351798
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a multiprocessor system and address resolution method therefor, and more particularly to a multiprocessor system featuring the distributed shared memory architecture and to address resolution method therefor.
Compared with a system where all memory is provided in one location, a system featuring the distributed shared architecture which distributes memory among multiple processors gives the user fast access to local memory. However, when multiple memories located at different locations are organized into one memory space in the distributed shared memory configuration, it is necessary to check whether a requested access is to a local memory or to a remote memory and, when the access request is to a remote memory, it must be transferred to the requested remote memory. This requires some means for resolving addresses (e.g., an address translation table).
A system with a typical distributed shared memory configuration usually has a plurality of configuration units (hereinafter called “cells”), each having computer's main components such as processors and memories, interconnected with each other to form a large system. In this case, it is relatively easy to separate each cell and run it as an independent computer. This separation is called “partitioning”, and a separated cell is called “a partition” or “domain”. This configuration gives an advantage over a centralized memory system in that a large system can be built easily.
On the other hand, in a large symmetric multiprocessor computer in which multiple processors share memory, there are software constraints and resource competitions that make it difficult to increase performance in proportion to the number of processors (scalability). There is also a physical limitation on the number of processors that can be added. To cope with these problems, multiple computers are sometimes interconnected to build a system which provides large processing power. A system like this is called “a cluster system”, and the independent computers constituting the cluster system are called “nodes”. The cluster system allows the user to build a system of any size and, in addition, ensures availability. That is, in many cases, the cluster system having multiple computers, each operating independently, prevents an error or a crash generated in one location of the system from affecting the whole system. For this reason, the cluster system is sometimes used to build a system which requires high reliability.
The problems with the cluster system described above is that the setup and the management of the system is more complex than a single computer of the same size and that the cabinets and cables require additional costs. To solve these problems, an “in-box” cluster system is on the market today. In this system, multiple already-interconnected small computers are installed in one cabinet and the setup and test are made before shipping. However, conventional cluster systems, including the “in-box” cluster system, use a network for computer interconnection. This results in a large communication overhead, sometimes preventing performance from increasing as more nodes are added.
On the other hand, added processors do not always increase the performance of a large single computer depending upon the processing it performs. In addition, an error or a failure, once caused in a large single computer, sometimes affects the whole system.
SUMMARY OF THE INVENTION
The present invention seeks to solve the problems associated with the prior art described above. It is an object of the present invention to provide a computer system, featuring the distributed shared memory architecture, which selectively acts as a single symmetric multiprocessor computer system or as an “in-box” cluster system. The computer with this configuration solves the problems with, and takes advantage of, the symmetric computer system and the “in-box” cluster system depending upon processing to be performed.
According to one aspect of the present invention, there is provided a multiprocessor system having a plurality of cells each including at least one processor and at least one memory, wherein the multiprocessor system determines a cell including the memory indicated by a specified address and inhibits a write request if destination of the request is some other cell.
REFERENCES:
patent: 4694396 (1987-09-01), Weisshaar et al.
patent: 5574849 (1996-11-01), Sonnier et al.
patent: 62-67665 (1987-03-01), None
patent: 3-132845 (1991-06-01), None
patent: 9-146903 (1997-06-01), None
patent: 9-179771 (1997-07-01), None
Japanese Office Action dated Oct. 31, 2000 with partial translation.
McGinn & Gibb PLLC
NEC Corporation
Pan Daniel H.
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