Semiconductor integrated circuit

Details Semiconductor integrated circuit Semiconductor integrated circuit

2000-06-23

2002-11-19

Zweizig, Jeffrey (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Specific identifiable device, circuit, or system

With specific source of supply or bias voltage

Reexamination Certificate

active

06483374

ABSTRACT:

TECHNICAL FIELD
The present invention relates to a semiconductor IC unit, more particularly to a semiconductor IC unit provided with both fast operation and low power consumption properties.
The present application follows part of the U.S. patent application Ser. No. PCT/JP97/04253 filed on Nov. 21, 1997. The contents of the preceding U.S. patent application are cited and combined with the present application.
BACKGROUND ART
At present, CMOS integrated circuits (IC) are used widely to form a semiconductor IC unit such as a microprocessor, etc. A CMOS IC consumes an electric power in two ways; dynamic power consumption and static power consumption. The dynamic power consumption is caused by charging and discharging at a switching time and the static power consumption is caused by a subthreshold leakage current. The dynamic power consumption consumes a large current in proportion to the square of a supply voltage VDD, so the supply voltage should be lowered to save the power consumption of the object CMOS IC effectively. In recent years, the supply voltage is thus getting lower and lower to cope with such an object.
On the other hand, some of the power-saving microprocessors available at present are provided with a power management feature and its processor is provided with a plurality of operation modes, so that supply of the clock to an active unit is stopped at its standby time according to the set operation mode.
Since the supply of the clock is stopped such way, it is possible to reduce unnecessary dynamic power consumption in such an active unit as much as possible. However, the static power consumption caused by a subthreshold leakage current cannot be reduced and still remains on the same level at this time.
The operation speed of a CMOS circuit drops at a low supply voltage. In order to prevent such a speed reduction of a CMOS circuit, therefore, the threshold voltage of the MOS transistor must be lowered in conjunction with the drop of the supply voltage. If a threshold voltage is lowered, however, the subthreshold leakage current increases extremely. And, as the supply voltage is getting lower, the static power consumption increases more remarkably due to the subthreshold leakage current, which has not been so much conventionally. This is why it is now urgently required to realize a semiconductor IC unit such as a microprocessor, which can satisfy both fast operation and low power consumption properties.
In order to solve the above problem, for example, the official gazette of Unexamined Published Japanese Patent Application No. Hei-6-54396 has proposed a method for controlling a threshold voltage of MOS transistors by setting a variable substrate bias.
The substrate bias is set to the power source potential for PMOS (P-channel MOS transistors) and the ground potential for NMOS (N-channel MOS transistors) in the active state when the object CMOS circuit is required for a fast operation. On the other hand, in the standby state in which the CMOS is not required for any fast operation, the substrate bias is set to a potential higher than the supply voltage for PMOS and lower than the supply voltage for NMOS (hereafter, this operation will often be referred to as “applying a bias voltage to a substrate”).
With such a setting of a substrate bias voltage in the standby state, it becomes possible to raise the threshold level of the MOS transistors composing the object CMOS circuit, thereby reducing the static power consumption caused by a subthreshold leakage current.
DISCLOSURE OF INVENTION
In order to materialize a semiconductor IC unit such as a microprocessor, etc., which can satisfy both fast operation and lower power consumption properties, the substrate bias must be controlled as described above for each CMOS circuit so that the threshold voltage of the MOS transistors is lowered when the semiconductor IC unit is active and raised when the semiconductor IC unit stands by, thereby reducing the subthreshold leakage current.
As a result of examination, however, the present inventor has found that the following problems still remain unsolved when in controlling the substrate bias in an actual semiconductor IC unit.
(1) A substrate bias controlling circuit must be tested easily as ever.
(2) A CMOS circuit must be prevented from malfunction by controlling the substrate bias.
(3) An increase of a circuit area must be minimized by controlling the substrate bias.
(4) A semiconductor IC unit must be prevented from malfunction when the substrate bias is switched over.
In order to solve the above problems, the present invention has proposed the following means mainly.
To make it easier to test the substrate bias controlling circuit, the output of the negative voltage generating circuit is connected to a pad. In other words, the negative voltage generating circuit must be checked for if a preset voltage level is reached as its output signal. For this check, the negative voltage generating circuit should be provided with a terminal from which the signal is output as it is.
In order to lower the substrate impedance, a plurality of substrate MOS transistors are provided in the main circuit used for controlling the substrate bias. The substrate driving MOS transistors are used to drive the substrate bias when the semiconductor IC unit is active. This is because the impedance must be lowered to fix the substrate potential and suppress the variance of the transistor threshold level when the IC circuit is active, thereby enabling the respective circuits in the main circuit to operate.
The driving power of the semiconductor IC unit increases in the active state more than in the standby state. Preferably, the driving power should thus be 5 times. Ideally, it should be 10 times that in the standby state.
Usually, each circuit becomes unstable when the substrate bias is switched over. In order to prevent this, the gate control signal used for controlling the gate voltage of a substrate driving MOS transistor is wired so that the control signal, after being connected to the substrate driving MOS transistor, is returned to the substrate bias controlling circuit and the potential of the returned signal is used by the substrate bias controlling circuit to detect that the main circuit substrate bias is stabilized.
The semiconductor IC unit is provided with a power-on resetting circuit. The power-on resetting circuit detects that the main circuit is powered. The semiconductor IC unit is kept in the active state so that each substrate driving MOS transistor drives the substrate bias shallowly for a fixed time after the main circuit is powered.
While the semiconductor IC unit is shifted from the standby state to the active state, the substrate bias controlling circuit controls the output impedance of the gate control signal so as to become larger than the impedance to be set after the semiconductor IC unit enters the active state completely.
The semiconductor IC unit is also provided with a negative voltage generating circuit. The substrate bias controlling circuit controls the output impedance of the negative voltage generating circuit in the standby state so as to be smaller than the output impedance in the active state.
The main circuit comprises a plurality of cells. Those cells compose a power-supply net, which is powered by the first metal levels. Another power-supply net is formed with the second wiring layers, which are orthogonal to the first metal levels. And, a switch cell is disposed at each intersection point of the power-supply nets formed with the first and second wiring layers. The power-supply nets of the first and second wiring layers are connected to each other in the switch cells. A substrate driving MOS transistor described above is disposed in each of those switch cells.
The substrate bias supply line of a MOS transistor composing one of the above cells is formed with the first metal levels, which are in parallel to the power-supply net formed with the first metal levels, as well as by the second wiring layers in parallel to the power-supply net formed with the second wiring l

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