Static information storage and retrieval – Floating gate – Particular connection
Reexamination Certificate
2001-07-03
2002-10-15
Nelms, David (Department: 2818)
Static information storage and retrieval
Floating gate
Particular connection
C365S185160, C365S185200
Reexamination Certificate
active
06466479
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a non-volatile memory matrix, particularly of the EPROM type. Specifically, the present invention relates to a non-volatile memory matrix architecture having a virtual ground monolithically integrated on semiconductor, and includes a plurality of memory cells organized into matrix blocks or sectors, which are placed on rows and columns associated with respective row and column decoding circuits. The present invention also relates to a memory matrix having a small number of contacts.
BACKGROUND OF THE INVENTION
EPROM or Flash EPROM electronic memory devices integrated on a semiconductor material include a plurality of non-volatile memory cells organized into matrices. That is, the memory cells are organized into rows called word lines, and columns called bit lines.
Each non-volatile memory cell comprises a MOS transistor, in which the gate electrode placed over the channel region is floating. The gate electrode has a high D.C. impedance towards all the other terminals of the same cell and of the circuit in which the cell is inserted. The cell also comprises a second electrode, called a control gate electrode, which is driven by suitable driving voltage. The other transistor electrodes are the drain and source terminals.
The most recent developments in the field of non-volatile memories, particularly EPROM and FLASH memories, are directed to the increase of the storage capacity due to process architectures and/or innovative designs. In some cases old ideas, abandoned in the past because of technological immaturity, are re-proposed.
A first known approach used to increase the memory capacity of a memory matrix makes use of the so called multilevel cells, which can store several memory stages. Although this first approach is advantageous from different points of view, it has some drawbacks. In fact, the multilevel technique is quite elaborate and requires a particular architecture.
A second known approach is to use memory matrices having an architecture of the virtual ground type, that is, matrices of the contactless type. In this type of matrix technology the field oxide layer is not present in the matrix active area where the memory cells are formed. An example of this type of matrix is described in the U.S. Pat. No. 5,204,835. Although achieving its objective, not even this approach is without drawbacks. In fact, it is necessary to introduce selection transistors to correctly read cell groups belonging to the same row. Such transistors occupy a relevant portion of the available area on the integrated circuit.
SUMMARY OF THE INVENTION
An object of the present invention is to form a non-volatile memory matrix architecture for electronic memory devices integrated on semiconductor, and particularly, a virtual ground matrix, having structural and functional features which allows for a very high density and for obtaining circuit dimensions smaller than the devices formed according to the prior art.
This and other objects, features and advantages in accordance with the present invention are obtained by eliminating memory cell selection transistors, and by obtaining an insulation among the matrix column blocks due to insulation stripes which allow the use of traditional methods for the row and column decoding.
In particular, the non-volatile memory matrix architecture comprises a semiconductor substrate comprising a virtual ground monolithically integrated thereon, and row and column decoding circuits on the semiconductor substrate. A plurality of memory cells may be on the semiconductor substrate organized into matrix blocks placed on rows and columns of the row and column decoding circuits. Each memory cell may comprise a transistor comprising a source region and a drain region that are interchangeable. The non-volatile memory matrix architecture may further include at least one insulation stripe on the semiconductor substrate between adjacent matrix blocks, and the at least one insulation stripe is parallel to the columns.
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Le Thong
Nelms David
STMicroelectronics S.r.L.
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