Semiconductor memory device permitting improved integration...

Details Semiconductor memory device permitting improved integration... Semiconductor memory device permitting improved integration...

2001-11-09

2002-11-12

Ho, Hoai (Department: 2818)

Static information storage and retrieval

Addressing

Plural blocks or banks

C365S230060

Reexamination Certificate

active

06480437

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to semiconductor memory devices, and more particularly, to reading-related circuitry in a semiconductor memory device.
2. Description of the Background Art
In recent years, as the storage capacity of semiconductor integrated circuit devices has increased, the critical dimension (the minimum manufacturable size) of transistors which form memory cells in the devices has been reduced as well. This gives rise to the necessity of miniaturizing transistors which form peripheral circuits and interconnections as well as the necessity of miniaturizing those which form memory cells.
The miniaturization of transistors to form sense amplifiers used for sensing slight potential difference generated between a bit line pair at the time of reading out data from a memory cell means a decline in the current driving capability per transistor. Thus, time required for the sense amplifier circuit to driving input/output (hereinafter “I/O”) line pairs in the array to indirect peripheral circuits such as an I/O line pair to a main amplifier increases.
A so-called direct-sense scheme is known as a method for solving such a disadvantage. An example of the direct-sense scheme is shown in FIG.
30
.
The gates of transistors
902
and
904
receive the potential levels of data line pairs DL
1
and /DL
1
, respectively, the potential difference of which is amplified by a sense amplifier
900
according to the storage information of a selected memory cell.
The sources of transistors
902
and
904
are supplied with a ground potential through a transistor
906
having its gate potential controlled by read control signal iore.
Transistor
902
has its drain connected to a data line DL
2
through a transistor
908
having its gate potential controlled by a reading control signal iore. Meanwhile, transistor
904
has its drain connected to a data line /DL
2
through a transistor
910
having its gate potential controlled by reading control signal iore.
Data read out from a memory cell is transmitted to an indirect peripheral circuit
920
by data line pair DL
2
, /DL
2
.
Hereinafter, the circuit formed by transistors
902
to
910
will be called “a sub-amplifier”.
In such direct sense scheme, data line pair DL
1
, /DL
1
and data line pair DL
2
, /DL
2
are isolated by transistors
902
and
904
. As a result, the capacity driven by sense amplifier
900
is simply that of data line pair DL
1
, /DL
1
to transistors
902
and
904
, while data line pair DL
2
, /DL
2
are driven by the sub-amplifier.
More specifically, the capacity driven by sense amplifier
900
is restrained, which allows for accessing at a higher speed.
However, in order to further increase the accessing speed, the following problem will be encountered.
In the conventional configuration shown in
FIG. 30
, a sense amplifier itself is often provided at the position of the sub-amplifier described above.
Alternatively, such a sub-amplifier is often located at a crossing point of a sense amplifier band and a sub-word driver band (hereinafter referred to as “a cross point”).
FIG. 31
is a schematic block diagram of an example of such a configuration.
Referring to
FIG. 31
, there are provided a main row decoder
940
and a column decoder
950
corresponding to a memory mat
930
.
Memory mat
930
is divided into sub-blocks
936
by sense amplifier bands
932
and word driver regions
934
.
In this configuration, sub-amplifiers SUA are provided at cross points of local I/O line pairs in the row-direction and global I/O line pairs in the column direction.
Signal iore to control sub-amplifier SUA is generated by main row decoder
940
and transmitted in the row-direction to sub-amplifier SUA.
However, the data reading operation itself is the operation by the column-related circuitry, and therefore, a signal line to transmit signal iore provided in the row-direction and a column selecting line YS to transmit a column selecting signal are perpendicular to each other. When column selecting line YS and the path to transmit signal iore are provided perpendicular to each other, a timing margin should be secured between the signals in view of skew between the signals, which impairs the accessing time from being reduced.
The miniaturization of a transistor forming sub-amplifier SUA increases sub-threshold leakage current by the transistor, and the power consumption disadvantageously increases by a constant amount of leakage current generated, even if the circuit is in a stand-by state, in other words, if transistor
906
is in a disconnected state.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a semiconductor memory device which permits accessing time to be improved in a large scale integrated semiconductor memory device.
Another object of the present invention is to provide a synchronous semiconductor memory device which permits the power consumption in a stand-by state to be reduced.
Briefly stated, a semiconductor memory device according to the present invention includes a memory cell array, a row selecting circuit, a column selecting circuit, a plurality of sense amplifiers, a plurality of sub-I/O line pairs, a selecting gate circuit, a main I/O line pair, and a plurality of sub-amplifiers.
The memory cell array includes a plurality of memory cells arranged in a matrix of rows and columns. The memory cell array includes a plurality of memory cell blocks. The row selecting circuit selects a corresponding memory cell row in response to an address signal. The column selecting circuit selects a corresponding memory cell column in response to an address signal.
The plurality of sense amplifiers are provided corresponding to memory cell columns in each memory cell block to amplify data from a selected memory cell.
The plurality of sub-I/O line pairs are provided corresponding to the plurality of memory cell blocks. The selecting gate circuit transmits reading data from a sense amplifier corresponding to a selected memory cell column in response to a column selecting signal transmitted in the memory cell column direction from the column selecting circuit. The main I/O line pair is provided in common to the plurality of memory cell blocks.
The plurality of sub-amplifiers transmit reading data transmitted from a sub-I/O line pair to the main I/O line pair. Each sub-amplifier includes first and second MOS transistors which each receive the potential of a sub-I/O line for a corresponding gate and discharge the corresponding main I/O line pair from a second potential to a first potential, an activation circuit which responds to a row-related control signal transmitted in the row direction of the memory cells and a column-related control signal transmitted in the column direction of the memory cells to activate the first and second transistors to perform discharging operation.
A semiconductor memory device according to another aspect of the present invention includes a memory cell array, a plurality of sense amplifiers, a plurality of I/O line pairs, a plurality of precharge circuits, a plurality of sub-amplifiers, and a segment signal line.
The memory cell array includes a plurality of memory cells arranged in a matrix of rows and columns. The memory cell array is divided into a plurality of memory cell blocks arranged in a matrix of rows and columns.
The plurality of sense amplifiers are provided corresponding to memory cell columns in each memory cell block to amplify data from a selected memory cell as complementary signals.
Each of the I/O line pairs is provided in common to at least two of memory cell blocks. The precharge circuits precharge I/O line pairs to a first potential. The plurality of sub-amplifiers are provided corresponding to the sense amplifiers to transmit read data to the I/O line pairs. Each of the sub-amplifiers includes first and second MOS transistors which have gates to receive complementary signals from a sense amplifier corresponding to said selected memory cell and discharge a corresponding one line of I/O line p

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