Register and latch circuits

Details Register and latch circuits Register and latch circuits

2000-04-07

2002-06-18

Tran, Toan (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Particular stable state circuit

C327S211000

Reexamination Certificate

active

06407604

ABSTRACT:

TECHNICAL FIELD
The present invention relates generally to semiconductor integrated circuits, and more particularly to register and latch circuits.
BACKGROUND OF THE INVENTION
The operating speeds of semiconductor devices continue to rise. Many integrated circuits include input circuits for latching input data. For example, many semiconductor devices are “synchronous” devices that latch input data in synchronism with a system clock. In addition, many integrated circuits can include output circuits that latch output data in response to a system clock. Still further, some integrated circuits have intermediate pipelined sections that may latch and/or shift data in response to a system clock. As device speeds increase, it can be important to reduce the time required for all aspects of device operation, including the time required to latch an input signal, and/or an output value and/or latch values in intermediate pipelined stages.
The operation of the disclosed embodiments may best be understood by first referring to a conventional register circuit.
FIG. 7
shows a conventional register circuit. The conventional register circuit is designated by the general reference character
700
and may include a master latch
702
and a slave latch
704
. A master latch circuit
702
can have an input (IN) that receives an input value, and can latch data in response to a clock signal CLK. A slave latch
704
can have an output (OUT) that provides a latched value, and can also latch data in response to the clock signal CLK.
A master latch circuit
702
can store data when the CLK signal has a low level. In addition, with the CLK signal level low, the output of the master latch circuit
702
is prevented from being input into the slave latch circuit
704
.
In the above-described arrangement, when the CLK signal transitions high, the input IN is disconnected from the internal circuits of the master latch circuit
702
. At the same time, the output of master latch circuit
702
is input to the slave latch circuit
704
, and provided as an output from the slave latch (OUT).
In synchronous devices, the clock signal CLK transitions between levels in a periodic fashion. Thus, in the example described above, each low-to-high transition can result in an output value at the output (OUT).
Next, the particular composition of a latch circuit will be described in more detail.
FIG. 7
shows the details of slave latch circuit
704
. A slave latch circuit
704
may include an input connected to the output of master latch circuit
702
. The input of the slave latch circuit
704
can be further connected to the source-drain paths of a p-channel metal-oxide-semiconductor (PMOS) transistor M
71
arranged in parallel with an n-channel MOS (NMOS) transistor M
72
. The gate of NMOS transistor M
72
receives the clock signal CLK, while the gate of PMOS transistor M
71
receives an inverted clock signal /CLK by way of an inverter INV
71
.
The slave latch circuit
704
further includes an inverter INV
72
for driving the output of the slave latch
704
(and hence the register
700
) in this case. The inverter INV
72
can have an input connected to the source-drain paths of transistors M
71
/M
72
, and an output connected to output OUT. An inverter INV
73
has an input connected to the output OUT, and an output connected to the source-drain paths of a PMOS transistor M
73
arranged in parallel with an NMOS transistor M
74
. The gate of NMOS transistor M
74
receives the inverted clock signal /CLK by way of inverter INV
71
, while the gate of PMOS transistor M
73
can receive the clock signal CLK directly.
In the slave latch circuit
704
illustrated, when the clock signal CLK is high, transistors M
71
and M
72
are turned on while transistors M
73
and M
74
are turned off. Thus, the output from master latch
702
can be driven on output OUT by inverter INV
72
. In contrast, when the clock signal CLK is low, transistors M
71
and M
72
are turned off while transistors M
73
and M
74
are turned on. The data at the output OUT can be fed back through inverter INV
73
to the input of inverter INV
72
, thus forming a flip-flop. In this way, the data value can continue to be held (latched) in the slave latch circuit
704
.
In a conventional integrated circuit, a register circuit may have adjacent circuits that can present large loads. More particularly, an input register circuit may have an output connected to an internal driver circuit that drives various internal lines of the integrated circuit. An output register circuit may have an output connected to an output driver circuit that outputs data from the integrated circuit. Such large loads can add to signal propagation times.
Further, the load that must be driven by the clock signal can also be high. More particularly, while the clock signal CLK of
FIG. 7
is shown driving two latch circuits (
702
and
704
), such a clock signal CLK may have to drive many such circuits.
One way to improve the speed in a conventional register circuit has been to attempt to reduce the input capacitance for the clock signal CLK. Gate capacitance can be reduced by decreasing the gate size of transistors M
72
and M
73
and the gates of transistors within inverter INV
71
. Such an approach can have limits, however. Reducing the size of transistors M
72
and M
73
can increase the “on” impedance of their respective transfer gates, increasing signal propagation time. Further, decreasing the size of transistors within inverter INV
71
can reduce the driving strength of the inverter, which can further reduce the speed at which the transfer gates can turn on and off.
In addition to operating speed, another feature of an integrated circuit that may be considered valuable is that of current consumption. Lower current consumption can be desirable as power supplies may have limited current supply capabilities. Further, lower current consumption can translate directly into lower power consumption. Reductions in power consumption are particularly desirable in portable electronic devices that operate on batteries.
Yet another important feature of an integrated circuit is the amount of area that is required for such a circuit. The more area that an integrated circuit requires, the more expensive the device may be to manufacture.
It would be desirable to arrive at some way of improving the speed of a latching and/or register circuit. Such a faster circuit could contribute to a faster overall integrated circuit.
It would also be desirable if such a circuit did not significantly increase power and/or current consumption over conventional approaches.
It would be further desirable if such a circuit did not require a considerable amount of area over conventional approaches.
SUMMARY OF THE INVENTION
A register circuit according to the present invention may include a master latch circuit and a slave latch circuit arranged in series with one another. A slave latch circuit may include a first driver transistor that can drive an output node to a first potential and a second driver transistor that can drive the output node to a second potential. A first controllable impedance path can connect the control terminal of the first driver transistor to the output of the master latch circuit. A second controllable impedance path can connect the control terminal of the second driver to the output of the master latch circuit. The first and second controllable impedance paths can be enabled according to a clock signal.
The above arrangement, the controllable impedance paths can transfer an input signal to the respective driver transistor control terminals, and not a flip-flop type circuit, and thus may allow for faster operating speeds.
According to one aspect of the embodiments, the controllable impedance paths may include transistors, more particularly, insulated gate field effect transistors. Further, the transistor of the first controllable impedance path can have a conductivity that is different from the first driver transistor. Similarly, the transistor of the second controllable impedance path can have a conductivity

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