Semiconductor memory

Details Semiconductor memory Semiconductor memory

2000-03-31

2002-06-11

Le, Vu A. (Department: 2824)

Static information storage and retrieval

Addressing

Plural blocks or banks

C365S189050, C365S230080, C365S230060

Reexamination Certificate

active

06404692

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to semiconductor memories, particularly to a semiconductor memory such as a synchronous dynamic random-access memory (to be referred to as SDRAM hereinafter) having a cell array including banks and capable of independently controlling these banks.
2. Description of the Related Art
In a semiconductor memory such as SDRAM, one chip is divided into banks, which are controlled independently of each other.
FIG. 1
shows a timing chart when four banks (Bank
0
to Bank
3
) are individually controlled.
In this timing chart of
FIG. 1
, the state of a block in each bank is always an active or pre-charge state, and these active and pre-charge states are alternately switched. In the active state, a predetermined block in a bank is activated to enable data read and write. In the pre-charge state, a block in an activated bank is restored to the state before being activated.
When a bank is in the active state, a specific word line in the bank rises to enable data write or read to a particular memory cell connected to this word line. In the pre-charge state, no word line rises, so neither data write nor read to a memory cell in the bank is possible.
FIG. 1
shows a case in which the pre-charge and active states are switched most frequently when write and read operations to a memory are performed. A block in each bank is set in the active state when receiving active commands (ACT
0
to ACT
3
) and in the pre-charge state when receiving pre-charge commands (PRE
0
to PRE
3
).
Operations of each bank are as follows. Operations performed in the active state are: (A
1
) “block selection” for selecting a sense amplifier column to be activated; (A
2
) “word line selection” for selecting a word line in a block; and (A
3
) “sense amplifier activation” for amplifying read data. Operations performed in the pre-charge state are: (P
1
) “word line reset” for setting a word line in a non-selected state; and (P
2
) “block selection release” for setting a sense amplifier in a non-active state and resetting a bit line to a standby state.
A semiconductor memory having four banks can receive each command in a cycle shown in FIG.
1
. In a period indicated by {circle around (
1
)} in
FIG. 1
, while an operation for switching bank
0
(Bank
0
) from the pre-charge state to the active state is performed, a pre-charge operation of bank
2
(Bank
2
) is started, and the active state of bank
3
(Bank
3
) and the pre-charge state of bank
1
(Bank
1
) are maintained. In a period indicated by {circle around (
2
)}, while a pre-charge operation of bank
3
(Bank
3
) is performed, an active operation of bank
2
(Bank
2
) is started, and the active states of bank
0
(Bank
0
) and bank
1
(Bank
1
) are maintained.
In SDRAM as described above, while the present state of a bank is maintained, a desired block in another bank can be switched to the active state, and a block in still another bank can be switched to the pre-charge state. That is, the banks can be operated and controlled independently of each other.
To this end, circuits such as sense amplifiers and sub-word drivers arranged in a cross portion, called an SS-Cross portion, between a sense amplifier group and a sub-word decoder group and various circuits for controlling these circuits must be so designed as to be able to control these banks independently.
FIG. 2
is a block diagram showing the arrangement of a cell array block of SDRAM for performing a four-bank operation.
FIGS. 3A and 3B
are schematic views showing details of the interior of the cell array shown in FIG.
2
. The arrangement of SDRAM for performing a four-bank operation will be briefly described below with reference to
FIGS. 2
,
3
A, and
3
B. Banks (Bank
0
to Bank
3
)
50
to
53
are provided with word drivers (wd)
54
to
57
as power generators for independently controlling these banks and setting a word line of a desired block in the active state. These word drivers
54
to
57
supply a main WD select signal (mwd) to the adjacent banks
50
to
53
. The banks
50
to
53
are also provided with main word decoders (mwdec)
58
to
61
. These main word decoders
58
to
61
are connected to main select lines (mwl).
A word line is selected as follows in each of these banks
50
to
53
. That is, in accordance with an input row address, the main word decoders
58
to
61
select a desired main select line (mwl). Also, a sub-word decoder (swdec in
FIGS. 3A and 3B
) driven on the basis of an output main WD select signal (mwd) from the word drivers
54
to
57
selects a desired one of sub-select lines (swl), which belongs to the selected main select line (mwl). Additionally, by selecting a bit line (not shown) in accordance with an input column address, a memory cell at the intersection of the word line and the bit line is selected.
FIG. 3A
is a view showing, in an enlarged scale, the internal arrangement of one bank (e.g., Bank
0
) in the SDRAM shown in FIG.
2
.
FIG. 3B
is a view showing, in a further enlarged scale, a sub-WD signal generator (swdgen)
64
and a sub-word decoder (swdec)
65
connected to this sub-WD signal generator
64
arranged in a cross portion (SS-Cross portion) between a sub-word decoder group (swdecs)
62
and a sense amplifier group (senseAmps)
63
shown in FIG.
3
A.
The bank is divided into blocks (four blocks as indicated by the dotted lines in mwdec shown in
FIG. 2
) along the word line direction. As shown in
FIG. 3A
, in each block cell array units are formed with sub-word decoder groups
62
and sense amplifier groups
63
perpendicular to each other. Sub-select lines (swl) run from the opposing sub-word decoder groups
62
in an interdigitated pattern. The sense amplifier groups
63
have a function of amplifying an output from a bit line (not shown) running in a direction perpendicular to the sub-select lines (swl). On these sense amplifier groups
63
, block signal lines for transmitting block select signals (blk
0
, blk
1
, . . .) run in the direction that the sense amplifier groups
63
run.
The sub-WD signal generator
64
shown in
FIG. 3B
includes an OR gate
64
a
for performing OR operation of select signals (blk
0
and blk
1
) of adjacent blocks, a NAND gate
64
b
for performing NAND operation of the output from the OR gate
64
a
and the main WD select signal (mwd) from the word driver
54
, and an inverter
64
c
for inverting the output from the NAND gate
64
b.
Complementary signals at the input and output of this inverter
64
c
are sub-WD select signals (swdz and swdx).
Each of these complementary sub-WD select signals (swdz and swdx) generated by the sub-WD signal generator
64
are input to sub-word decoders
65
connected to this sub-WD signal generator
64
. Of these sub-word decoders
65
, a sub-word decoder
65
connected to a main select line (mwl) selected by the main word decoder
58
activates a sub-select line (swl). Consequently, a desired memory cell is selected, and data write or read is performed.
FIG. 4
is a timing chart showing signals for controlling the bank
50
(Bank
0
) and the bank
51
(Bank
1
). Major ones of these signals shown in
FIG. 4
will be described below. When the bank
50
accepts the active command (ACT
0
), a signal bras
0
z rises. This signal bras
0
z indicates whether the bank is in the active state or the pre-charge state. During a period in which the corresponding bank is in the active state, the signal bras
0
z maintains “H”. Upon receiving this “H” status signal bras
0
z, a block select signal (blkz) of a block to which a memory cell to be selected belongs, rises.
Also, when receiving the “H” status signal bras
0
z, a main WD select signal (swl) selected in accordance with a row address rises. Additionally, the sub-WD signal generator
64
activates the sub-WD select signals (swdz and swdx) by logically operating the “H” main WD select signal (mwd) and the block select signal (blkz).
A main select line (mwl) falls to “L” when selected by the main word decoder
58
in accordance with a row address. T

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