Multiple ISA support by a processor using primitive operations

Details Multiple ISA support by a processor using primitive operations Multiple ISA support by a processor using primitive operations

1998-07-21

2002-08-20

Follansbee, John A. (Department: 2154)

Electrical computers and digital processing systems: processing

Instruction decoding

Reexamination Certificate

active

06438679

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to the field of processors. More specifically, the present invention relates to the subject matter of processor instruction set architectures (ISA).
2. Background Information
Every processor has an ISA. The term ISA as used herein refers to the aspects of a processor that are visible to a programmer or compiler writer, wherein the term processor as used herein is intended to include micro-controllers (MCU), digital signal processors (DSP), general purpose microprocessors (&mgr;P), and the like. The ISA of the various processors known in the art can be differentiated by the type of internal storage provided by the processor for instruction operands, the number of explicit operands named per instruction, whether instruction operands can be located outside the processor, the various operations provided, the type and size of the operands, and so forth.
Historically, implementation of an ISA is accomplished through the control logic provided to a processor to control the processor's datapath in performing arithmetic logic operations, which is typically specific for the ISA to be implemented. The term datapath as used herein is intended to be a collective reference to the processor elements employed in performing arithmetic logic operations. In the case of prior art processors, prior art datapath typically includes arithmetic logic unit(s) (ALU), operand register file, various control registers and so forth. The control logic is provided either through hardwired logic or microprogramming (also referred to as microcode or firmware). In the case of hardwired logic, typically one or more random control logic block are employed to generate the proper control signals to be output to control the datapath. The proper control signal to be output at a particular clock cycle is selected based on the current state of the processor, feedback from the datapath and the opcode of the next instruction to be executed. In the case of microprogramming, typically microinstructions are employed to specify the control signals for the datapath. The microinstructions are stored e.g. in a read-only-memory (ROM), and selected for output in each clock cycle, based on the current microinstruction program counter (PC). At each clock cycle, the microinstruction PC is modified based on a newly computed next microinstruction PC, the current microinstruction output (specifying in part the next microinstruction to be output), feedback from the datapath, and/or the opcode of the next instruction to be executed (also referred to as the next macroinstruction).
Some prior art successor processors, for legacy reasons, would accept complex instruction set computer (CISC) instructions of an historic ISA, and decode them into reduced instruction set computer (RISC) instructions of a new internal ISA for execution, even though the processors are designed with more modern RISC principles. Typically, the new internal ISA is designed to specifically mimic the historic ISA. The processor is provided with a decoder to handle the conversion between the two architectures, and control logic is equipped to control the datapath to specifically implement the new internal ISA. Instructions of the internal ISA are issued to the datapath using a micro-instruction program counter.
These prior art approaches to implementing an ISA and controlling a processor's datapath suffer from a number of disadvantages. First and foremost, each processor is capable of executing only one ISA. Much of the control logic of a processor would have to be redesigned if the processor is to be adapted to support a different or a new ISA. Except for enhancements and extensions to an existing ISA, the industry almost never adapt a processor to support a different or a new processor, because of the amount of redesign effort would have been required. Virtually all processors supporting a new ISA are considered to be new designs. As a result, the industry is often confronted with significant conversion effort to adopt a more powerful new processor, executing a new ISA, to replace a number of less powerful older processors, executing their respective old ISA. Alternatively, the conversion effort becomes a significant roadblock to the wider acceptance or deployment of the more powerful new processor. For example, in many applications it is actually more price/performance effective to use anyone of a number of newer general purpose microprocessors, then to continue to use an older DSP in combination with an older MCU, but for the conversion cost of the legacy code.
Thus, a more effective approach to ISA implementation and controlling a processor's datapath without some of the prior art disadvantages is desired.
SUMMARY OF THE INVENTION
A processor is provided with a datapath and control logic to control the datapath to selectively effectuate execution of instructions of multiple ISA.
In some embodiments, execution of the instructions of the different ISA are effectuated by selectively executing primitive operations (POP) of different ISA implementing POP collections. Among some of these embodiments, the POP of each collection are hierarchically organized.
In some embodiments, the processor further includes at least one ISA selector accessible to the control logic to facilitate the control logic in controlling the datapath to selectively effectuate execution of the instructions of the different ISA. Among some of these embodiments, the at least one ISA selector facilities the control logic in controlling the datapath to selectively effectuate execution of instructions of the different ISA in different deployments of the processor. In other embodiments, the at least one ISA selector facilities the control logic in controlling different sets of resources of the datapath to selectively effectuate execution of instructions of the different ISA. In yet other embodiments, the at least one ISA selector facilities the control logic in controlling a set of resource of the datapath to selectively effectuate execution of instructions of different user instruction streams that are of different ISA. In yet other embodiments, the at least one ISA selector facilities the control logic in controlling a set of resource of the datapath to selectively effectuate execution of instructions of different portions of a user instruction streams that are of different ISA.
In some embodiments, the processor further includes an ISA library. Among some of these embodiments, the ISA library stores and supplies different collections of primitive operations implementing instructions of the different ISA. In other embodiments, the ISA library also stores and supplies other control information for the different ISA, such as logical to physical mappings.


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