Coded data generation or conversion – Analog to or from digital conversion – Analog to digital conversion
Reexamination Certificate
2001-05-08
2002-11-12
Wamsley, Patrick (Department: 2819)
Coded data generation or conversion
Analog to or from digital conversion
Analog to digital conversion
C341S118000
Reexamination Certificate
active
06480136
ABSTRACT:
FIELD OF INVENTION
This invention relates to an integrated circuit having repetitive cells with repetitive output circuits designed to be matched for proper, accurate circuit operation, and more particularly to such an integrated circuit having means to reduce the adverse effects of output circuit mismatch as well as cell mismatch.
BACKGROUND OF INVENTION
There are many integrated circuits which include a large number of repetitive cells designed to perform in matched fashion so as to assure specified circuit performance. Such cells often include impedance elements such as resistors which are for example supplied by current sources to produce corresponding output signals. Analog-to-digital (A/D) and digital-to-analog (D/A) converters are examples of devices which frequently incorporate such repetitive cells.
One problem which often arises with such integrated circuits is that in a practical device the actual match between cells turns out to be less than wanted, so that the device performance is less than satisfactory. For example, in A/D converters of the flash type, mismatch between repetitive cells typically forming part of the comparators conventionally used in such converters will adversely affect the differential and integral linearity of the outputs. Thus, in any group of processed monolithic chips having such integrated circuits, the number of parts meeting specifications for high-grade performance may be much smaller than desired due to random mismatches caused by small deviations from nominal in the parameters of some of the circuit elements. Attempts have been made to solve this problem of mismatch between repetitive cells in an integrated circuit.
In one approach, the cells all include resistors (of equal ohmic value) carrying currents (designed to be of equal value) producing corresponding output signals. To avoid the effects of cell mismatch on the output signals, a network of equal-valued resistors is added to the circuit, with each network resistor connected between corresponding ends of adjacent pairs of the cell resistors as disclosed in U.S. Pat. No. 5,175,550. This works well with respect to accommodating for cell mismatches, but in actual application each cell has associated with it one or a pair of output circuits such as a level shifting circuit or a driver circuit which also must be properly matched in order to obtain desired precision.
BRIEF SUMMARY OF THE INVENTION
It is therefore an object of this invention to provide an integrated circuit which reduces the adverse effect of output circuit mismatch as well as cell mismatch.
It is a further object of this invention to provide such an integrated circuit which reduces the adverse effect of output circuit mismatch as well as cell mismatch with few additional components.
It is a further object of this invention to provide such an integrated circuit which reduces the adverse effect of output circuit mismatch as well as cell mismatch with a simple impedance network.
The invention results from the realization that the adverse effects of both cell mismatch and associated output circuit mismatch in a repetitive cell integrated circuit can be reduced using an impedance to form circuitry which modifies the effective output of the cell and of the output circuit.
This invention features an integrated circuit including a number of repetitive cells for producing output signals in response to respective inputs. Each of the cells includes a circuit element having two terminals to provide for the flow therethrough of a current from an associated current source and producing a corresponding cell output signal. An impedance network includes a set of impedance elements each connected between the corresponding terminals of respective pairs of the circuit elements with each circuit element of the pairs forming part of respective cell. The impedance elements permit the flow of current therethrough to reduce the effects of cell mismatch on the output signals. An output circuit is associated with each cell; each output circuit includes a circuit device having two terminals to provide for the flow therethrough of a current from an associated current supply and produces a corresponding output signal. The improvement for reducing the effects of output circuit mismatch includes a second impedance network having a second set of impedance elements each connected between corresponding terminal of respective pairs of the circuit devices, with each circuit device of such pairs forming part of a respective output circuit. The second impedance elements permit the flow of current therethrough to reduce the effects of output circuit mismatch on the output signals.
This invention also features an integrated circuit including a number of repetitive cells for producing output signals in response to respective inputs. Each cell has associated with it an output circuit responsive to the cell output signal to produce an output circuit output signal. Each of the output circuits includes a circuit device having two terminals to provide for the flow therethrough of a current from an associated current supply and produces a corresponding output circuit output signal. The improvement for reducing the effects of cell mismatch and output circuit mismatch includes an impedance network having a set impedance elements each connected between corresponding terminals of respective pairs of the circuit devices. Each circuit device of such pairs forms a part of a respective output circuit. The impedance elements reduce the effects of cell mismatch and output circuit mismatch on the output signals.
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M. Choi & A. Abidi, “A6b 1.3GSample/s A/D Converter in 0.35 &mgr;m CMOS,” IEEE ISSCC Digest of Technical Papers, p. 126-127 and Visuals Supplement, pp. 96-97, 405, IEEE, 2001.
Jarman David
Kranz Rodney Louis
Lane Charles D.
Analog Devices Inc.
Iandiorio & Teska
Wamsley Patrick
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