Semiconductor device manufacturing: process – Chemical etching – Vapor phase etching
Reexamination Certificate
1999-07-30
2002-10-08
Utech, Benjamin L. (Department: 1765)
Semiconductor device manufacturing: process
Chemical etching
Vapor phase etching
C438S710000, C438S712000
Reexamination Certificate
active
06461968
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method for fabricating a semiconductor device, and more specifically, to a method for fabricating a TFT substrate to be used in a display device such as a liquid crystal display device.
2. Description of the Related Art
TFTs (thin film transistors) are used for driving a display device such as a liquid crystal display device.
FIG. 4
shows a partial plan view of a TFT substrate fabricated in accordance with a conventional fabrication method of a semiconductor device.
FIGS. 5A
to
5
J show cross-sectional views each illustrating the process steps in the conventional fabrication method of the semiconductor device of FIG.
4
. Among these drawings,
FIG. 5J
is a cross-sectional view taken along line X—X in
FIG. 4
, and
FIGS. 5A
to
5
I show cross-sectional views at the corresponding position in the respective process steps.
As shown in
FIGS. 4 and 5J
, a TFT substrate
600
used in a liquid crystal display device includes a gate interconnection
63
patterned on a substrate
61
, a gate insulating film
62
made of silicon nitride and formed on the entire surface of the substrate
61
so as to cover the gate interconnection
63
, an intrinsic semiconductor layer
64
and an n-type semiconductor layer
65
sequentially deposited on the gate insulating film
62
in the shape of islands. The intrinsic semiconductor layer
64
and the n-type semiconductor layer
65
are in particular referred to as a semiconductor layer structure. Furthermore, a base layer
66
and a top layer
67
are provided as source interconnection materials (including a source electrode material and a drain electrode material) on the substrate
61
so as to cover the n-type semiconductor layer
65
. The base layer
66
and the top layer
67
are in particular referred to as a metal layer structure.
In the TFT substrate
600
, the base layer
66
and the top layer
67
form a source electrode
72
, a drain electrode
73
and a source interconnection
74
. A gap portion
71
for the transistor (hereinafter, referred to as “a transistor gap portion”) is formed between the source electrode
72
and the drain electrode
73
so as to run through the top layer
67
, the base layer
66
and the n-type semiconductor layer
65
and into the intrinsic semiconductor layer
64
.
In the TFT substrate
600
, ITO is used as a material of the base layer
66
of a source interconnection material. In the step of dry etching the top layer
67
, the base layer
66
of ITO is not etched. Therefore, the etching is performed without affecting the underneath portion already formed below the ITO film
66
since the ITO film
66
functions as a barrier. Thus, the patterning of the source interconnection is commonly done by separately performing etching of the top layer
67
on the ITO film
66
, etching of the ITO film
66
, and etching of the n-type semiconductor layer
65
and the intrinsic semiconductor layer
64
to form the transistor gap portion
71
.
Hereinafter, as a conventional fabrication method of the TFT substrate, a method of forming a source electrode, a drain electrode, a source interconnection (hereinafter, these are collectively referred to as “a source interconnection and the like”), and a transistor gap portion will be described with reference to
FIGS. 5A
to
5
J.
As shown in
FIG. 5A
, the gate interconnection
63
is patterned in a predetermined pattern on the substrate
61
, and the gate insulating film
62
is formed thereon. Then, the semiconductor layer structure including the intrinsic semiconductor layer
64
of amorphous silicon and the n-type semiconductor layer
65
of N
+
amorphous silicon are formed on the gate insulating film
62
in the shape of an island.
Next, as shown in
FIG. 5B
, the ITO film (base layer)
66
is formed on the resultant structure of
FIG. 5A
by sputtering or the like. Thereafter, the top layer
67
of a source interconnection material is formed on the resultant structure by sputtering or the like, as shown in FIG.
5
C.
Next, a resist layer is provided on the top layer
67
by a spin coat method, or the like. The resist layer is then patterned by photolithography to form a first photoresist pattern
68
, as shown in FIG.
5
D.
Next, as shown in
FIG. 5E
, portions of the top layer
67
not covered by the first photoresist pattern
68
are removed by a chemical liquid treatment or dry etching. In this step, the first photoresist pattern
68
functions as a mask, so that the other portions of the top layer
67
covered with the first photoresist pattern
68
are unremoved. Furthermore, the entire underlying ITO film
66
is not substantially etched away because an etching select ion ratio thereof with respect to the top layer
67
is infinite. It should be noted that when the etching (patterning) of the top layer
67
is performed by dry etching in this step, etching residues (not shown) from the top layer
67
remain.
Next, as shown in
FIG. 5F
, the first photoresist pattern
68
is removed by a chemical liquid treatment. When the top layer
67
has been dry etched to be patterned in the previous step, the aforementioned etching residues are also removed by this chemical liquid treatment.
Next, another resist layer is provided on the patterned top layer
67
by a spin coat method or the like, and then patterned by a photolithography method so as to form a second photoresist pattern
69
, as shown in FIG.
5
G.
Next, as shown in
FIG. 5H
, portions of the ITO film
66
not covered by the second photoresist pattern
69
are removed by a chemical liquid treatment or dry etching. During this step, the second photoresist pattern
69
functions as a mask, so that the other portions of the ITO film
66
covered by the second photoresist pattern
69
are not removed. It should be noted that when the ITO film
66
is removed by dry etching in this step, etching residues (not shown) from the ITO film
66
are left on the n-type semiconductor layer
65
.
Next, as shown in
FIG. 5I
, the second photoresist pattern
69
is removed by a chemical liquid treatment. When the ITO film
66
has been etched by dry etching to be patterned in the preceding step, the aforementioned etching residues are also removed by this chemical liquid treatment. Thus, a source interconnection and the like are formed.
Next, a portion of the N
+
amorphous silicon layer
65
is removed by dry etching. Furthermore, the amorphous silicon layer
64
is partly removed by dry etching at a position corresponding to the removed portion of the N
+
silicon layer
65
. Finally, residues or the like generated during the above dry etching steps are removed by a chemical liquid treatment, thereby forming the transistor gap portion
71
, as shown in FIG.
5
J.
Thus, the TFT substrate
600
is fabricated.
In the above described conventional method for fabricating a TFT substrate, an ITO film is used for a base layer to be a source interconnection and the like. A top layer, which is to be a source interconnection and the like, is made of a metal material such as aluminum, an aluminum alloy, titanium, titanium compound including titanium nitride, chromium, tungsten, and a mixture thereof. An etchant for etching the top layer is selected in accordance with a material for the top layer. For example, when a material for the top layer is one of an aluminum-group material, a molybdenum-group material, and a tungsten-group material, a mixture of phosphoric acid, acetic acid and nitric acid, or the like is used. When a material for the top layer is a titanium-group material, hydrofluoric acid or the like is used. When a material for the top layer is a tantalum-group material, a mixture of hydrofluoric acid and nitric acid is used. Furthermore, a photoresist pattern functioning as a mask is made of a resin or the like.
In the step of etching the top layer made of the aforementioned material and provided above the ITO film, the portion of the underlying layered structure disposed below the ITO film is advantageously prevented fro
Itoh Kenji
Toyota Motohiro
Nixon & Vanderhye P.C.
Perez-Ramos Vanessa
Sharp Kabushiki Kaisha
Utech Benjamin L.
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