Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor – Incorporating resilient component
Reexamination Certificate
2000-03-07
2002-11-26
Graybill, David E. (Department: 2827)
Semiconductor device manufacturing: process
Packaging or treatment of packaged semiconductor
Incorporating resilient component
C438S118000
Reexamination Certificate
active
06486003
ABSTRACT:
FIELD OF THE INVENTION
The present invention generally relates to microelectronic assemblies, and more specifically it relates to components which facilitate connections between a microelectronic element such as a semiconductor chip and external circuit elements.
BACKGROUND OF THE INVENTION
Connection components such as interposers and/or substrates are typically used in combination with microelectronic elements such as semiconductor chips to facilitate electrical interconnections between semiconductor chips and external circuit elements. The reliability of the entire circuit operation depends upon the electrical connections between the chip, the interposer and the external circuit elements.
Various attempts have been made to produce connections between the chip and the external circuit elements satisfying the above discussed requirements. For example, commonly assigned U.S. Pat. No. 5,148,265, the disclosure of which is incorporated herein by reference, discloses an advanced method for providing the connection between a semiconductor chip and external circuit elements. According to certain embodiments discussed in the '265 patent, a semiconductor chip is connected to a corresponding substrate through a dielectric interposer. The semiconductor chip has a plurality of peripheral contacts positioned in a peripheral area of a front surface thereof. The flat, flexible interposer is formed with a plurality of connecting terminals, each of which is connected to a bonding terminal adjacent the periphery of the interposer. The flexible interposer is supported by a compliant layer. The peripheral contacts of the semiconductor chip are connected to the terminals of the interposer by bonding a multiplicity of fine leads to the chip. In one embodiment, the lead-bonding operation uses fine wires which are bonded to bonding terminals on the periphery of the interposer and to the contacts of the chip. During a wire bonding operation, when downwardly directed forces are applied to the peripheral region of the interposer containing the bonding terminals, this area of the interposer flexes downwardly. The downward movement of the interposer in the area of the bonding terminals may impede the bonding of the wires and the bonding terminals.
Commonly assigned U.S. patent application Ser. No. 08/709,127, the disclosure of which is hereby incorporated by reference, discloses a structure for compliantly interconnecting semiconductor chips and supporting substrates while substantially obviating problems associated with thermal cycling. In one preferred embodiment, the semiconductor chip package includes a sheet-like substrate having one or more gaps extending from a first surface to a second surface of the substrate and conductive terminals which are contacted from the second surface of the substrate. The substrate further has conductive leads electrically connected to and extending from each terminal and across the one or more gaps. Each lead is connected to a bond pad on the opposite side of the gap so that each lead has an expansion section within the gap which is laterally curved with respect to the plane of the substrate. In certain preferred embodiments, the expansion sections laterally curve at least twice in opposite directions and in one particular embodiment creates substantially “S” shaped lead portions. This structure allows the package to compensate for coefficient of thermal expansion (“CTE”) mismatch problems by the flexing and bending of the expansion sections of the leads within the one of more gaps. The expansion sections of the leads are typically encapsulated with a compliant encapsulant to provided added support for their bending and flexing motion during thermal cycling.
Commonly assigned U.S. patent application Ser. No. 08/516,645, filed Aug. 18, 1995, the disclosure of which is incorporated herein by reference, discloses a microelectronic assembly comprising an interposer having oppositely facing first and second surfaces, a connecting terminal region and a bonding terminal region. The interposer has connecting terminals on the second surface in the connecting terminal region and has bonding terminals in the bonding terminal region. The assembly also includes a microelectronic element such as a semiconductor chip or other element having a front surface and having contacts on the front surface. The interposer overlies the front surface of the semiconductor chip with the second surface of the interposer facing upwardly away from the chip and with the first surface facing downwardly toward the chip. The connecting terminals are movable relative to the chip in vertical directions, whereas the bonding terminals are supported against such vertical movement. The interposer preferably comprises a thin, flexible layer, and a compliant layer disposed between the flexible layer and the chip for movably supporting the connecting terminal region. The assembly according to this aspect of the invention desirably also includes a reinforcing structure for reinforcing the bonding terminal region of the flexible layer against vertical movement towards the semiconductor chip. Subassemblies according to this aspect of the invention can be subjected to a bonding operation, such as a wire bonding operation, in which flexible conductors such as bonding wires are connected between the bonding terminals and the contacts on the chip. Because the bonding terminal region is reinforced, the bonding operation can be conducted efficiently. However, the finished assembly still provides the benefits associated with a compliantly mounted interposer, including testability and compensation for thermal effects during operation.
In spite of the advanced methods for providing the connection between a semiconductor chip and external circuit elements, further improvements would be desirable.
SUMMARY OF THE INVENTION
One aspect of the present invention provides a method of fabricating a microelectronic package. A method in accordance with this aspect of the invention includes the steps of providing first and second microelectronic elements having electrically conductive parts, providing an expandable structure disposed between the microelectronic elements, connecting the electrically conductive parts of the microelectronic elements together so that the microelectronic elements are electrically interconnected and expanding the expandable structure after the connecting step whereby the expandable structure increases in size so that the microelectronic elements move away from one another during the expanding step. During the connecting step, one or more flexible wires or leads are provided for electrically interconnecting the conductive parts. After the connecting step, the leads preferably have sufficient slack therein so that the microelectronic elements remain electrically interconnected during the expanding step.
In certain preferred embodiments, the expandable structure comprises a thermoplastic film or thermoplastic elastomer and a foaming agent, such as a high temperature foaming agent. The foaming agent is preferably a high temperature foaming agent so that foaming is not inadvertently triggered during processing of the package elements. The expandable structure may also comprise polypropylene with a toluene sulfonyl semicarbazide or another high temperature foaming agent, such as 5-phenyl tetrazole. As will be explained in more detail below, the expandable structure is substantially rigid during the connecting step and substantially flexible or pliant after the expanding step. During the expanding step, a sufficient amount of heat is applied to the expandable structure so that the thermoplastic film or thermoplastic elastomer will soften and the foaming agent will vaporize, causing the thermoplastic film to foam and expand. As the expandable structure expands, platens are preferably abutted against external surface regions of the microelectronic elements to maintain substantial parallelism between the microelectronic elements and to control the overall thickness of the expandable structure. In one embodiment
Graybill David E.
Lerner David Littenberg Krumholz & Mentlik LLP
Tessera Inc.
LandOfFree
Expandable interposer for a microelectronic package and... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Expandable interposer for a microelectronic package and..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Expandable interposer for a microelectronic package and... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2969997