Active solid-state devices (e.g. – transistors – solid-state diode – Housing or package – Insulating material
Reexamination Certificate
2000-04-28
2002-02-05
Graybill, David E. (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Housing or package
Insulating material
C257S730000, C257S738000, C257S713000
Reexamination Certificate
active
06344685
ABSTRACT:
TECHNICAL FIELD OF THE INVENTION
The present invention relates in general to techniques for mounting semiconductor devices to substrates, and more particularly to a technique that reduces adverse mechanical stresses between the device and the substrate caused by changes in temperature.
BACKGROUND OF THE INVENTION
Electrical semiconductor devices in the form of a “die” are generally mounted on a substrate during the final stages of assembly. It is generally known that a substantially planar bottom surface of an electrical semiconductor device can be mounted to a substantially planar top surface of the substrate by the use of a mechanical bonding agent, such as solder. The substrate provides mechanical support for the electrical device, and may be utilized to connect the electrical device to a ground potential. Various surface structures are known to be used when mounting a semiconductor device to a substrate. For instance, the substrate surface may possess finely dimpled, abraded areas, or grooves to assist with mechanically securing the electrical component to the substrate.
Typically, the semiconductor device or die is fabricated with silicon, germanium, galium arsenide, or other similar material. The substrate is usually constructed of a metal or ceramic material. The substrate material is generally selected for thermal conduction properties to efficiently transfer the heat from the semiconductor material to the substrate. The heat is dissipated from the substrate via pins, heatsink structures, or to the atmosphere.
Because many semiconductor devices generate heat as a result of current passing through resistive paths, such heat must be dissipated in a manner that does not adversely affect the long-term reliability of the device. The heat generated within the device is not the only source of heat, as heat applied to chips during soldering processes can also damage the structures. If the temperature changes are substantial and the two materials are of vastly different thermal coefficients of expansion, the parts undergo stress either during the heating stage or the cooling stage, or both.
Lastly, internal thermal energy can be applied to devices by externally applied electrical currents, such as in the case with overvoltage or overcurrent protection devices. An overvoltage caused by lightning or a power line cross can cause substantial current to flow through the protective devices. The large currents can cause a significant amount of heat within the devices, and can cause mechanical or physical destruction, especially in semiconductor chips that are soldered to metal or ceramic substrates. Because of the differing thermal expansion characteristics of such electrical devices, the mechanical shock caused by the thermal heating of the device can cause stresses in the material of such a magnitude that can crack or break the components.
During electrical operation of the semiconductor device, the temperature of the electrical semiconductor device rises, and often significantly, due to the I
2
R losses. As the temperature of the electrical semiconductor device increases, the temperature of the solder and the substrate will also increase. As a result, the solder will expand and the physical size and shape of both the electrical semiconductor device and the substrate may change. It is of critical importance that the thermal stresses experienced do not damage either the semiconductor die or the substrate. However, because different materials are selected to achieve the vastly different purposes, there generally exists a significant difference in the thermal coefficients of expansion of the materials. With the different expansion of solder as well as the deformation of the semiconductor device and the substrate, mechanical stresses are created between the substrate and the semiconductor device. The degree of material expansion between the semiconductor material and the substrate increases with increasing temperature.
Various attempts have been made to reduce the effects of mechanical stresses between semiconductor dies attached to substrates. U.S. Pat. No. 5,150,197 discloses a technique for distributing the stress between a semiconductor die and a substrate having a solder joint therebetween. According to the patent, a more uniform temperature distribution is achieved when the solder joint varies in thickness, with the thicker portion being near the edge of the semiconductor chip, and thinner near the center of the chip where the temperature generated by the chip is the greatest. With this arrangement, the stress in the solder joint is minimized. Also, the substrate was formed with a central pedestal that either had rounded comers, or had a convex surface on which the chip was mounted. Because of the contoured or curved profile and shape of the substrate pedestal, and the corresponding shape of the solder therebetween, the stress vectors between the substrate and the semiconductor chip are not all unidirectional. Rather, due to the curvature in the solder connection, thermal stresses yet exist in the semiconductor chip when the substrate expands. However, there is no suggestion in the patent of how to reduce the stresses in the attachment of different materials, based on the particular materials involved and the temperature range involved.
It can be seen from the foregoing that a need exists for a better technique in attaching a semiconductor chip to a non-semiconductor substrate so as to further reduce the stresses induced therein when subjected to temperature changes. Another need exists for a method for ascertaining to a high degree of reliability the optimum surface shape between a semiconductor chip and a substrate, based on the particular thermal coefficients of expansion thereof.
SUMMARY OF THE INVENTION
In order to reduce the physical stresses between semiconductor devices and the substrates to which they are attached, one object of the present invention is to mount the device on a conical shaped pedestal portion of the substrate. The conical pedestal has a flat top surface with a substantially uniform declining slope from a center area to the edge of the substrate. That is, the declining slope of the mounting surface extends in a substantially uniform manner from a high point at the center of the substrate to a lower exterior edge of the side portion of the substrate. If an appropriate angle is chosen for the substantially uniform declining slope, the lateral stresses of expansion between the materials during a temperature cycle are greatly reduced.
Various pedestal shapes may be chosen, which preferably include a smooth conical structure. The center of the substrate pedestal may also include a pointed apex or a small flat mounting surface near the center to facilitate assembly and mounting of the semiconductor device to the substrate. If the small flat mounting surface near the center is employed, a substantially uniform declining slope preferably extends from the edge of the flat region to the lower exterior edge of the side portion of the substrate. The conical-shaped surface is necessary only on that portion of the pedestal where solder flows to attach the parts together.
When the semiconductor device is mounted on the conical pedestal, the solder fillet therebetween exhibits stress vectors that are all vertical, thus reducing thermal stresses in the materials. In accordance with an important feature of the invention, the angle between the underside of a semiconductor chip and the conical surface of the substrate pedestal is calculated as a function of the thermal coefficients of expansion of the materials. Thus, the angle can be selected to ideally achieve the minimum stress induced into the structure as a result of temperature cycling of the device.
REFERENCES:
patent: 3791019 (1974-02-01), Schmidt
patent: 3821614 (1974-06-01), Schmidt
patent: 4151546 (1979-04-01), Kawagai et al.
patent: 4258382 (1981-03-01), Harris
patent: 4263606 (1981-04-01), Yorikane
patent: 4413308 (1983-11-01), Brown
patent: 4434434 (1984-02-01), Bhattacharya et al.
patent: 4604644 (1986-08-01
McCoy Carol G.
McCoy Dennis M.
Chauza & Handley, L.L.P.
Graybill David E.
McCoy Carol G.
Teccor Electronics, LP
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