Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Chip mounted on chip
Reexamination Certificate
1999-11-30
2002-06-25
Talbott, David L. (Department: 2827)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Chip mounted on chip
C257S723000, C257S784000, C257S691000, C257S676000, C257S684000, C257S685000, C257S686000, C257S690000, C257S692000, C361S813000
Reexamination Certificate
active
06410987
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device and, more particularly, to a technique advantageously applied to a semiconductor device in which two semiconductor chips are stacked on one another and are encapsulated with a single resin encapsulant.
2. Description of the Related Art
For the purpose of increasing the capacity of a storage circuit system, stacked semiconductor devices have been proposed in which two semiconductor chips forming a memory circuit system are stacked on one another and are encapsulated with a single resin encapsulant. For example, Japanese unexamined patent publication No. H7(1995)-58281 discloses a stacked semiconductor device having a LOC (lead on chip) structure.
A stacked semiconductor device having a LOC structure is comprised of a first semiconductor chip and a second semiconductor chip having a plurality of electrode pads formed on a circuit forming surface thereof which is the top surface, i.e., one of principal surfaces opposite to each other, a plurality of first leads bonded and secured to the circuit forming surface of the first semiconductor chip with an insulating film interposed therebetween and electrically connected to the electrode pads on the circuit forming surface through conductive wires, a plurality of second leads bonded and secured to the circuit forming surface of the second semiconductor chip with an insulating film interposed therebetween and electrically connected to the electrode pads on the circuit forming surface through conductive wires and a resin encapsulant for encapsulating the first semiconductor chip, second semiconductor chip, inner portions of the first leads, inner portions of the second leads, the wires and the like. The first and second semiconductor chips are stacked with their circuit forming surfaces facing each other. The first and second leads are bonded with respective connecting portions overlapping each other.
The inventors have encountered the following problems in the course of the development of stacked semiconductor device.
The conventional LOC structure as described above results in an increase in manufacturing cost because the manufacture involves the use of two lead frames when this structure is adopted.
The above-described conventional technique necessitates two lead frames because two semiconductor chips are to be stacked.
Further, since two semiconductor chips are stacked, the electrode pads of the two semiconductor chips can not be provided in four directions on the semiconductor chips with a single lead frame.
It is therefore an object of the invention to provide a technique which makes it possible to reduce the thickness of a semiconductor device by stacking two semiconductor chips and encapsulating the two semiconductor chips with a single resin encapsulant.
It is another object of the invention to provide a technique that accommodates a structure of a semiconductor device having two semiconductor chips stacked and encapsulated with a single resin encapsulant in which a single lead frame serves electrode pads provided along four sides of the stack formed by the two semiconductor chips.
It is still another object of the invention to provide a technique to make it possible to provide a multi-chip package having a reduced mounting without changing the storage capacity.
It is still another object of the invention to provide a technique that makes it possible to prevent cracks in a structure of a semiconductor device having two semiconductor chips stacked and encapsulated with a single resin encapsulant.
The above and other objects and novel features of the invention will be clearly understood from the description of this specification and the accompanying drawings.
SUMMARY OF THE INVENTION
Typical aspects of the invention disclosed in this specification can be briefly summarized as follows.
(1) There is provided a semiconductor device comprising:
a first semiconductor chip having a circuit forming surface and a back surface opposite to the circuit forming surface and a plurality of electrode pads formed on the circuit forming surface;
a second semiconductor chip having a circuit forming surface and a back surface opposite to the circuit forming surface and a plurality of electrode pads formed on the circuit forming surface and having a plane size greater than that of the first semiconductor chip;
a plurality of leads each having an inner portion and an outer portion, the inner portions being electrically connected to respective electrode pads of the first and second semiconductor chips through conductive wires;
a support lead having an inner portion and an outer portion for supporting the second semiconductor chip with the inner portion; and
a resin encapsulant for encapsulating the first semiconductor chip, the second semiconductor chip, the inner portions of the leads, the inner portion of the support lead and the wires, wherein
the first semiconductor chip is bonded and secured to the second semiconductor chip with the back surface of the first semiconductor chip and the circuit forming surface of the second semiconductor chip facing each other and wherein
the inner portion of the support lead is bonded and secured to the circuit forming surface of the second semiconductor chip.
(2) There is provided a semiconductor device according to the first aspect, wherein a part of the inner portions of the leads is provided on the circuit forming surface of the second semiconductor chip.
(3) There is provided a semiconductor device comprising:
a first semiconductor chip having a circuit forming surface and a back surface opposite to the circuit forming surface and a plurality of electrode pads formed on the circuit forming surface;
a second semiconductor chip having a circuit forming surface and a back surface opposite to the circuit forming surface and a plurality of electrode pads formed on the circuit forming surface and having a plane size greater than that of the first semiconductor chip;
a plurality of leads each having an inner portion and an outer portion, the inner portions being electrically connected to respective electrode pads of the first and second semiconductor chips through conductive wires;
a support lead having an inner portion and an outer portion for supporting the second semiconductor chip with the inner portion; and
a resin encapsulant for encapsulating the first semiconductor chip, the second semiconductor chip, the inner portions of the leads, the inner portion of the support lead and the wires, wherein
the first semiconductor chip is bonded and secured to the second semiconductor chip with the back surface of the first semiconductor chip and the back surface of the second semiconductor chip facing each other and wherein
the inner portion of the support lead is bonded and secured to the back surface of the second semiconductor chip.
(4) There is provided a semiconductor device comprising:
a first semiconductor chip having a circuit forming surface and a back surface opposite to the circuit forming surface and a plurality of electrode pads formed on the circuit forming surface;
a second semiconductor chip having a circuit forming surface and a back surface opposite to the circuit forming surface and a plurality of electrode pads formed on the circuit forming surface and having a plane size greater than that of the first semiconductor chip;
a plurality of leads each having an inner portion and an outer portion, the inner portions being electrically connected to respective electrode pads of the first and second semiconductor chips through conductive wires;
a support lead having an inner portion and an outer portion for supporting the first and second semiconductor chips with the inner portion; and a resin encapsulant for encapsulating the first semiconductor chip, the second semiconductor chip, the inner portions of the leads, the inner portion of the support lead and the wires, wherein
the first semiconductor chip is bonded and secured to the second semiconductor chip with the back surface of the first semicondu
Kanemoto Kouichi
Kimura Mikako
Masuda Masachika
Sugiyama Michiaki
Wada Tamaki
Hitachi , Ltd.
Mattingly Stanger & Malur, P.C.
Talbott David L.
Thai Luan
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