Overlay alignment mark design

Details Overlay alignment mark design Overlay alignment mark design

2000-06-22

2002-10-08

Evans, F. L. (Department: 2877)

Optics: measuring and testing

By alignment in lateral direction

With registration indicia

C356S400000, C430S022000

Reexamination Certificate

active

06462818

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates generally to the testing of semiconductor wafers during the production of the wafer. More specifically, the present invention relates to the use of a new alignment pattern to determine the registration accuracy between two patterned layers on a semiconductor wafer.
BACKGROUND
One of the most critical process control techniques used in the manufacturing of integrated circuits is the measurement of overlay accuracy between successive, patterned layers on a wafer (i.e., the determination of how accurately a patterned layer aligns with respect to the layer above or below it).
Presently this measurement is done with test patterns that are etched into the layers. The relative displacement is measured by imaging the patterns at high magnification on an electronic camera using any of a variety of known image analysis algorithms. The most commonly used patterns are concentric squares with dimensions of approximately 20 micrometers on each side, generally referred to as “box within a box” target.
FIG. 1
illustrates a typical “box” type target
5
. Inner box
1
is typically printed on the top layer of the semiconductor wafer being produced, while the open-center-outer block
2
is printed on the second layer down on the semiconductor wafer. The measurement process thus involves imaging of target
5
on an electronic camera, by means of a microscope system, at a high magnification (1000×, typically) and with high resolution in both x and y directions.
The registration error in each of the x and y axes is measured by first calculating the locations of the edges of lines c
1
and c
2
of the outer box
2
, and the edge locations of the lines c
3
and c
4
of the inner box
1
. The registration error represents the amount of misalignment between the two layers which are being tested. From those locations the registration error between the two boxes is determined by comparing the average separation between lines c
1
and c
3
with the average separation between lines c
4
and c
2
(i.e., the registration error between boxes
1
and
2
is the difference between those two separations). The registration error between boxes
1
and
2
in each axis is thus calculated using the following formulas:
R
x
=(
c
x
3
−c
x
1)−(
c
x
2
−c
x
4)  (1a)
and
R
y
=(
c
y
3
−c
y
1)−(
c
y
2
−c
y
4)  (1b)
Thus, if the average spacing between lines c
1
and c
3
is the same as the average spacing between lines c
2
and c
4
, the corresponding value of R in that axis will be zero.
This prior art is further described and analyzed by Neal T. Sullivan, “Semiconductor Pattern Overlay”, in Handbook of Critical Dimensions Metrology and Process Control, pp. 160-188, vol. CR52, SPIE Press (1993). The accuracy of the prior art is limited by the asymmetry of etched line profiles, by aberrations in the illumination and imaging optics, and by image sampling in the camera. It would be desirable to have a system that overcomes the limitations of the prior art.
SUMMARY
The present invention is directed to an apparatus and a method for measuring the relative position between two layers of a device. In one embodiment of the invention, the two layers are stacked layers in a semiconductor wafer. The apparatus uses a mark which includes at least one set of calibration periodic structures and at least two sets of test periodic structures, both types of which are positioned along an axis. Each set of test periodic structures has its periodic structures formed within first and second sections. The periodic structures of the first and second sections are each formed on one of the two layers of the device, respectively. The first and second sections of each test set are positioned proximate to the second and first sections of the next test set, respectively. This mark allows two beams which scan the mark to travel over both a test section formed on one layer of the device and a test section formed on the other of the two layers. Scanning multiple test sets provides multiple registration error values which are then averaged to obtain a registration error value that is minimally affected by asymmetries between the two beams used in the measurement process and/or asymmetries between the different layer characteristics (e.g., differences in height and/or differences in material composition between test sets of the two measured layers). The registration error represents the amount of misalignment between the two layers which are being tested.
Another aspect of the present invention is directed towards a method for measuring the relative position (e.g., alignment) between two layers of a device. The method begins by providing a first set of calibration periodic test structures and providing at least two sets of test periodic structures which have a structure similar to that of the mark described above. A beam is then scanned in a first path across portions of the calibration periodic structures and the sets of test periodic structures. A beam is then scanned in a second path across portions of the calibration periodic structures and the sets of test periodic structures. Signals are generated with respect to the portion of the beams which reflect off the surface of the device so that the registration error between the two layers in a specific direction may be calculated. This process may then be repeated in order to calculate the registration error between the two layers in a separate direction. Preferably, an average registration error is calculated between the two layers for each direction.
These and other features and advantages of the present invention will be presented in more detail in the following specification of the invention and the accompanying figures which illustrate by way of example the principles of the invention.


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