Semiconductor device having test mode

Details Semiconductor device having test mode Semiconductor device having test mode

2001-08-16

2002-12-24

Nguyen, Viet Q. (Department: 2818)

Static information storage and retrieval

Powering

C365S201000, C365S189090, C365S189110, C323S312000, C323S313000

Reexamination Certificate

active

06498760

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device and, more particularly, a semiconductor device having a test mode driven by an external power supply potential.
2. Description of the Background Art
Conventionally, in a dynamic random access memory (hereinbelow, abbreviated as DRAM), packing density is being increased and power supply voltage is being decreased. For this purpose, the DRAM is provided with an internal power supply potential generating circuit for generating an internal power supply potential by dropping the external power supply potential. In the DRAM, to reject an early defective piece in which a defect occurs relatively early after shipment, a burn-in test is carried out before shipment. In the burn-in test, an internal power supply potential higher than that in a normal mode is applied, and data is written/read to/from each of memory cells under high-temperature environment. It accelerates the occurrence of a defective, so that an early defective piece can be prevented from being shipped.
FIG. 10
is a block diagram showing the configuration of such an internal power supply potential generating circuit
80
of a DRAM. In
FIG. 10
, the internal power supply potential generating circuit
80
includes a VPP generating circuit
81
, a VDDS generating circuit
82
, and a VDDP generating circuit
83
.
The VPP generating circuit
81
includes, as shown in
FIG. 11
, a ring oscillator
84
, a charge pump circuit
85
, and a detector
86
. The detector
86
receives both a potential VPP of a power supply node N
85
and an internal power supply potential VDDS from the VDDS generating circuit
82
. When VPP<VDDS+2Vthn (where Vthn denotes a threshold voltage of an N-channel MOS transistor), the detector
86
sets a signal &phgr;E to the “H” level. When VPP≧VDDS+2Vthn, the detector
86
sets the signal &phgr;E to the “L” level. When the signal &phgr;E is at the “H” level, the ring oscillator
84
generates a clock signal CLK and supplies it to the charge pump circuit
85
. When the signal &phgr;E is at the “L” level, the ring oscillator
84
is made inactive. The charge pump circuit
85
supplies a predetermined amount of positive charges to the power supply node N
85
in response to the rising edge of the clock signal CLK.
When VPP<VDDS+2Vthn, the positive charges are supplied from the charge pump circuit
85
to the power supply node N
85
. When VPP≧VDDS+2Vthn, the supply of power from the charge pump circuit
85
to the power supply node N
85
is stopped. The potential VPP at the power supply node N
85
is therefore maintained at VDDS+2Vthn. The internal power supply potential VPP is used as a wordline selection level.
The VDDS generating circuit
82
includes, as shown in
FIG. 12
, an operational amplifier
90
, a constant current source
91
, a variable resistive element
92
, and P-channel MOS transistors
93
and
94
. The constant current source
91
and the variable resistive element
92
are connected in series between a line of the external power supply potential VCC and a line of a ground potential VSS. The P-channel MOS transistor
93
has the source for receiving an external reference potential VRS′, the drain connected to a node N
91
between the constant current source
91
and the variable resistive element
92
, and the gate for receiving a test signal ITE.
The P-channel MOS transistor
94
is connected between the line of the external power supply potential VCC and a power supply node N
94
. The operational amplifier
90
has an inversion input terminal connected to the node N
91
, a non-inversion input terminal connected to the power supply node N
94
, and the output terminal connected to the gate of the P-channel MOS transistor
94
. The operational amplifier
90
and the P-channel MOS transistor
94
construct a voltage follower for maintaining the potential VDDS at the power supply node N
94
at the same level as the potential at the node N
91
. The internal power supply potential VDDS is applied to a sense amplifier.
At the time of tuning, the test signal /TE is set to the “H” level as an inactivate level, and the P-channel MOS transistor
93
is made non-conductive. The resistance value of the variable resistive element
92
is tuned so that the internal power supply potential VDDS becomes equal to a predetermined value VRS.
At the time of a burn-in test, the test signal /TE is set to the “H” level as an activate level, the P-channel MOS transistor
93
is made conductive, and the internal power supply potential VDDS becomes equal to the external reference potential VRS′ (>VRS). The internal power supply potential VPPS becomes equal to VRS′+2Vthn. In normal operation, the test signal /TE is set to the “H” level as an inactivate level, the P-channel MOS transistor
93
is made non-conductive, and the internal power supply potential VDDS becomes VRS. The internal power supply potential VPP becomes equal to VRS+2Vthn.
The VDDP generating circuit
83
includes, as shown in
FIG. 13
, an operational amplifier
95
, a constant current source
96
, a variable resistive element
97
, P-channel MOS transistors
98
and
99
, an N-channel MOS transistor
100
, and an inverter
101
. The constant current source
96
and the variable resistive element
97
are connected in series between the line of the external power supply potential VCC and the line of the ground potential VSS. The P-channel MOS transistor
99
is connected between the line of the external power supply potential VCC and a power supply node N
98
. The operational amplifier
95
has an inversion input terminal connected to a node N
96
between the constant current source
96
and the variable resistive element
97
, a non-inversion input terminal connected to the power supply node N
98
, and an output terminal connected to the gate of the P-channel MOS transistor
99
. The operational amplifier
95
and the P-channel MOS transistor
99
construct a voltage follower which maintains the potential VDDP of the power supply node N
98
to the level same as the potential of the node N
96
. The internal power supply potential VDDP is supplied to peripheral circuits.
The P-channel MOS transistor
98
is connected in parallel with the constant current source
96
. The N-channel MOS transistor
100
is connected between the gate of the P-channel MOS transistor
99
and the line of the ground potential VSS. The test signal ITE is directly supplied to the gate of the P-channel MOS transistor
98
and also to the gate of the N-channel MOS transistor
100
via the inverter
101
.
At the time of tuning, the test signal /TE is set to the “H” level as an inactivate level, and the MOS transistors
98
and
100
are made non-conductive. The resistance value of the variable resistive element
97
is tuned so that the internal power supply potential VDDP becomes equal to a predetermined value VRP (>VRS).
At the time of a burn-in test, the test signal /TE is set to the “L” level as an activate level, the MOS transistors
98
and
100
are made conductive, and the internal power supply potential VDDP becomes equal to the external power supply potential VCC. In normal operation, the test signal /TE is set to the “H” level as an inactivate level, the MOS transistors
98
and
100
are made non-conductive, and the internal power supply potential VDDP becomes VRP.
In short, in normal operation, VPP=VRS+2Vthn, VDDS=VRS, and VDDP=VRP. At the time of the burn-in test, VPP=VRS′+2Vthn, VDDS=VRS′, and VDDP=VCC. VRS and VRP are tuned.
In the conventional internal power supply potential generating circuit
80
, however, VPP is equal to VDDS+2Vthn. Consequently, VPP and VDDS cannot be set independently of each other. Occurrence of an early defective in a circuit portion to which VPP is applied and that in a circuit portion to which VDDS is applied cannot be separately accelerated, so that test efficiency is low.
The resistance v

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