Multiplex communications – Pathfinding or routing – Switching a message which includes an address header
Reexamination Certificate
1998-11-05
2002-02-05
Kizou, Hassan (Department: 2662)
Multiplex communications
Pathfinding or routing
Switching a message which includes an address header
C370S465000
Reexamination Certificate
active
06345052
ABSTRACT:
FIELD
The present invention relates generally to digital broadband transmission systems, and more particularly, to a state machine architecture for the reliable transition of status signals when using a localized sampling architecture in an ATM-PHY interface device.
BACKGROUND
The Asynchronous Transfer Mode (ATM) protocol has been widely adopted to provide high-speed, low-delay multiplexing and switching networks to support any type of user traffic, including voice, data and video. ATM resides on top of the physical layer (PHY) of a conventional layered model, but does not require the use of a specific physical layer protocol. The PHY layer may be implemented using any of a number of interfaces and protocols, including SONET/SDH, DS
3
, FDDI and others.
At the ATM-PHY interface, the Universal Test & Operations PHY Interface for ATM protocol (commonly known as UTOPIA) has been accepted by the ATM Forum group as the protocol of choice to interconnect the ATM layer to the PHY layer. The ATM Forum's specifications for UTOPIA are found in AF-PHY-0017.000, “UTOPIA Specification”, Level 1, Version 2.01, Mar. 21, 1994. and in AF-PHY-0039.000, “UTOPIA, An ATM-PHY Interface Specification”, Level 2, Version 1.0, Jun. 1, 1995.
With the continuing expansion of digital broadband transmission systems, including ATM systems, there is growing demand for higher bus speeds between interoperable equipment. Maintaining satisfactory timing requirements at higher bus speeds can be difficult to meet and poses a challenge at the ATM-PHY interface. The ATM Forum's specification for UTOPIA defines timing requirements for ATM-PHY interfaces which must be satisfied to ensure interoperability when using UTOPIA. Timing requirements set by the UTOPIA specification can be difficult to meet, particularly at higher bus speeds. For instance, the 50 MHz UTOPIA bus allows for a maximum of 4 nanoseconds (ns) for input set-up times and 1 ns for input hold times.
Timing constraints such as those imposed by the UTOPIA specification can be particularly difficult to satisfy in multi-channel VLSI devices having an ATM cell processor for each channel. ATM cell processors are typically self-contained macro-cells designed to connect to the UTOPIA bus without separate resampling devices. ATM cell processors designed in this way have the advantage of being adaptive for use in single channel UTOPIA Level 1 compliant devices as well as with the UTOPIA level 2 bus. However, in such a self-contained architecture all circuits that sample the UTOPIA bus input signals reside within the ATM cell processor macro-cells. Locating sampling circuitry within each macro-cell of a multi-channel device has the disadvantage of making set-up and hold times difficult to satisfy as physical routing of the bus signals in the VLSI device is different for each of the ATM cell processors, resulting in variability in this top-level routing. Furthermore, the routing of the bus signals within each ATM cell processor macro-cell, also referred to as macro-cell routing, may not be very deterministic. The variability in routing delay arising from these circumstances makes it difficult to predict which signals will have the worst timing characteristics prior to the physical layout of the device, thereby increasing the number of layout iterations required to satisfy the timing constraints for the UTOPIA specification. In addition, typically delay elements are required in each path that the UTOPIA bus input signal takes before it is sampled. While delay elements may be measured and adjusted after each layout iteration to improve the performance of the circuit, the variability arising from the combination of top-level routing and macro-cell routing remains a problem which is difficult to remedy in such circumstances, even for a lower speed bus. The problem of variability in routing delay becomes even more pronounced with the tighter timing requirements of a higher speed bus such as the UTOPIA 50 MHz bus.
Apart from the need for a simplified architecture for satisfying the timing requirements at the ATM-PHY interface, it will be appreciated by persons skilled in the art that the UTOPIA interface requires zero wait-state reaction to its input control signals. Routing delays at both the top-level and within each macro-cell can contribute to timing problems when interfacing the ATM layer with PHY layers. As a result, an ATM cell processor macro-cell must predict the next state of the input signals from the UTOPIA bus in order that the ATM cell processor can configure its outputs accordingly so as to avoid the possibility of incorrect predictions resulting in lost cells or FIFO overruns. If input control signals from the UTOPIA bus do not behave as predicted, a timing mechanism must be provided to ensure that the output status signals from the ATM cell processor continue to perform correctly in such circumstances. It would be advantageous if such a timing mechanism would extend to both single-channel and multi-channel implementations. It would be also advantageous if such a timing mechanism would enable the ATM-PHY interface device to maintain set-up and hold timing constraints that are much tighter than those required by the UTOPIA standard for the ATM-PHY interface. This would allow systems interfacing with the ATM-PHY interface device the flexibility of having more relaxed timing, thereby reducing design cycle time and the cost at both the device and system level.
SUMMARY OF THE INVENTION
It is an object of the present invention to fulfill the aforementioned needs in the art for an improved architecture at the ATM-PHY interface. In the present invention there is provided an architecture which can be used to simplify the endeavor to satisfy the timing requirements at the ATM-PHY interface. The architecture is based on localizing and reducing the number of logic units which sample the input signals arriving at the ATM-PHY interface device from the UTOPIA bus.
In another aspect of the invention, there is provided a method and apparatus for handling incorrect predictions by the ATM-PHY interface device of incoming signals arriving at the ATM-PHY interface from the UTOPIA bus when using the localized sampling architecture. In one embodiment, a state machine is provided which serves as a conditioning circuit to ensure that incorrect predictions by the ATM-PHY interface device of the incoming UTOPIA compliant signals do not cause the ATM-PHY interface device to output transmit cell available signals out of synch with the UTOPIA protocol.
The invention may be applied to serve both single-channel and multi-channel ATM-PHY devices and can be used in both single-PHY and multi-PHY architectures adding further versatility to its application.
Advantageously, the architecture of the present invention allows for a simple deterministic layout procedure to be used which does not require extensive layout iterations to satisfy tight timing constraints such as those defined by the UTOPIA specification.
REFERENCES:
patent: 5784370 (1998-07-01), Rich
patent: 5889778 (1999-03-01), Huscraft et al.
patent: 6115360 (2000-09-01), Quay et al.
The ATM Forum Technical Committee, “Utopia Specification Level 1, Version 2.01”, Mar. 21, 1994.
The ATM Forum Technical Committee, “Utopia Level 2, Version 1.0”, Jun. 1995.
McDowell Shawn Patrick
Tse Richard Tsz-Shiu
Hall Priddy Myers & Vande Sande
Kizou Hassan
PMC-Sierra Ltd.
Spafford Tim
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