Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Amplitude control
Reexamination Certificate
1999-05-25
2002-10-08
Lam, Tuan T. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Amplitude control
C330S259000, C360S067000
Reexamination Certificate
active
06462600
ABSTRACT:
TECHNICAL FIELD
The invention relates generally to integrated circuits (ICs), and more particularly to an integrated read-head preamplifier circuit having an amplifier and an on-board offset compensator for the amplifier. In one embodiment, the amplifier is a differential amplifier.
BACKGROUND
To reduce the pin count and manufacturing costs of an IC and to reduce the assembly costs of products incorporating the IC, the IC designer typically designs the IC to require as few external components as possible. For example, suppose that the IC includes an amplifier that requires an external compensation capacitor. To accommodate the capacitor, the IC typically needs at least one pin that is “dedicated” to the capacitor. Unfortunately, in addition to increasing the IC's pin count, this dedicated pin often increases the package size and manufacturing complexity, and thus the manufacturing costs, of the IC. Furthermore, if the IC is installed on a circuit board of a computer disk drive, the external capacitor often increases the component count and assembly complexity of the circuit board, and thus often increases the disk drive's component and assembly costs.
FIG. 1
is a schematic block diagram of a read circuit
8
including a magneto-resistive read head
10
and an integrated preamplifier circuit
12
, which requires an external compensation capacitor
14
. The head
10
senses data written on a magnetic medium such as a magnetic disk (
FIG. 8
) and generates a read signal based on the values of the sensed data. The circuit
12
includes a bias circuit
16
for providing a bias signal to the head
10
, an amplifier
18
for amplifying the read signal from the head
10
, and a driver circuit
20
for interfacing the amplified read signal to other circuitry (FIG.
8
). As discussed below in conjunction with
FIGS. 2 and 3
, the external capacitor
14
allows the amplifier
18
to generate a balanced output signal in spite of the unbalanced bias voltage it receives from the head
10
.
FIG. 2
is schematic diagram of a circuit model for the read head
10
of FIG.
1
. The head
10
includes head input/output terminals
22
and
24
, and is modeled as a serial combination of an AC (nonzero frequency) voltage source
26
and equal-valued resistors
28
and
30
, and a capacitor
32
in parallel with the serial combination. In one embodiment of the head
10
, the resistors
28
and
30
each have a value of 25 ohms (Q) and the capacitor
32
has a value of 2 picofarads (pF).
In operation, the head
10
generates a bias voltage in response to a DC (zero or near-zero frequency) bias current from the bias circuit
16
(FIG.
1
). The bias current flows through the serial combination of the source
26
and resistors
28
and
30
and charges the capacitor
32
to a corresponding bias voltage that appears across the head terminals
22
and
24
. As the magnetic storage medium (
FIG. 8
) moves by the head
10
, the polarities of the stored magnetic fields—these fields represent the stored data—cause the voltage source
26
to generate a corresponding AC voltage Vread, which represents the data stored on the magnetic medium. The data is primarily represented by the Vread frequencies that are greater than or equal to approximately 1 Megahertz (MHz). Therefore, to reduce signal noise, the read channel (
FIG. 8
) coupled to the output of the preamplifier
12
typically filters out all frequencies below approximately 1 MHz. Furthermore, because the values of the resistors
28
and
30
are relatively small and the input impedance of the amplifier
18
is relatively large, one can approximate that the full value of Vread appears across the terminals
22
and
24
, and is thus superimposed on the DC head bias voltage. But although Vread is superimposed on the head bias voltage, one can easily recover Vread by removing the head bias voltage from the combined signal as discussed below.
FIG. 3
is a schematic diagram of a known differential version of the integrated preamplifier circuit
12
of FIG.
1
.
The bias circuit
16
includes a conventional current source
40
for generating a bias current for the head
10
, and includes a feedback circuit
42
for centering the head bias voltage around a reference voltage such as 0 Volts (V), i.e., ground. The feedback circuit
42
includes bias elements such as resistors
44
and
46
, which are in parallel with the head
10
and which define a sense node
48
. A high-gain differential amplifier such as an operational amplifier
50
compares the sense voltage at the sense node
48
with ground and controls the conductivity of a transistor
52
to maintain the sense voltage substantially equal to 0 V. The transistor
52
has its source coupled to a resistor
54
, and thus is configured as a common source stage. A resistor
56
and a capacitor
58
are coupled to the output of the amplifier
50
and set the dominant pole of the feedback circuit
42
. In one embodiment of the circuit
16
, the current source
40
generates a bias current of approximately 5 milliamperes (mA), the resistors
44
and
46
each have a value of approximately 5 kiloohm (K•), the transistor
52
is an NMOS transistor, the resistor
54
has a value of approximately 500&OHgr;, the resistor
56
has a value of approximately 500 K&OHgr;, the capacitor
58
has a value of approximately 20 pF, and the dominant pole is approximately 16 kilohertz (KHz).
The pseudo-differential cascoded amplifier
18
differentially receives the bias voltage and Vread from the head
10
(
FIG. 2
) on input terminals
60
and
62
. As discussed below, the amplifier
18
effectively filters out the bias voltage and amplifies only Vread to generate an intermediate differential read signal on output terminals
64
and
66
. The amplifier
18
includes current sources
68
and
70
, input transistors
72
and
74
, cascode transistors
76
and
78
, loads such as resistors
80
and
82
, and compensation terminals
84
and
86
. The cascode transistors
76
and
78
receive a bias voltage Vbias, which is generated by a conventional bias circuit (not shown). Because the amplifier
18
includes the two separate current sources
68
and
70
instead of a single, shared current source, the amplifier
18
is not a true differential amplifier; hence the name “pseudo-differential.” But as discussed below, having separate current sources allows the amplifier
18
to effectively filter the DC head bias voltage from the input signal, and the compensation capacitor
14
allows the amplifier
18
to differentially amplify Vread. In one embodiment of the amplifier
18
, the current sources
68
and
70
each generate a respective current of approximately 3 mA, the transistors
72
,
74
,
76
, and
78
are bipolar NPN transistors, the resistors
80
and
82
each have a value of approximately 1.6 K&OHgr;, and the external capacitor
14
has a value of approximately 0.01 microfarads (&mgr;F).
Still referring to
FIG. 3
, the output driver circuit
20
receives the intermediate differential read signal from the amplifier output terminals
64
and
66
and generates an output differential read signal on output terminals
88
and
90
. The drive circuit
20
includes drive transistors
92
and
94
and respective current sources
96
and
98
. In one embodiment of the drive circuit
20
, the transistors
92
and
94
are bipolar NPN transistors and the current sources
96
and
98
each generate a respective current of approximately 1 mA.
Referring to
FIGS. 2 and 3
, the steady-state and data-read operations of the preamplifier
12
are discussed. “Steady-state” refers to the preamplifier operation in response to input signals having low and zero frequencies (e.g. head-bias voltage), and “data-read” refers to the preamplifier operation in response to input signals having higher frequencies (e.g. Vread). For example, using the component and current-source values given above for the head
10
and the preamplifier
12
, steady-state corresponds to frequencies less than or equal to approximately 16 KHz, and data-read cor
Jorgenson Lisa K.
Lam Tuan T.
Santarelli Bryan A.
STMicroelectronics Inc.
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