Coded data generation or conversion – Sample and hold
Reexamination Certificate
2001-06-22
2002-06-18
Tokar, Michael (Department: 2838)
Coded data generation or conversion
Sample and hold
C327S091000, C327S094000, C327S095000, C341S122000, C341S123000
Reexamination Certificate
active
06407687
ABSTRACT:
TECHNICAL FIELD
The present invention relates generally to electrical circuits, and more particularly to a system and method for reducing timing mismatch in sample and hold circuits.
BACKGROUND OF THE INVENTION
Analog to digital converters (ADCs) are important analog circuit devices which take an analog input signal and generate one or more digital signals which are representative of the analog input. ADCs are used in many applications such as communications applications in which the components receive a voice input (an analog input) and transform the voice date into a digital format for internal processing. Exemplary applications using such ADCs are illustrated in prior art
FIGS. 1 and 2
, respectively. For example, in prior art
FIG. 1
, an exemplary base transceiver station (BTS)
10
is illustrated in which an RF analog input signal
12
is received, amplified and converted into a digital signal
14
before being processed in a baseband section
16
and network interface section
18
. Similarly, prior art
FIG. 2
illustrates a schematic diagram of an automobile multimedia system
20
in which various analog signals such as radio signals
22
and sensor signals
24
are transformed into digital signals for subsequent processing. Further, many other system applications exist, including, but not limited to, hard disk drive (HDD) read channel applications.
One of the most challenging portions of an ADC is the sample and hold (S/H) circuit at the front end thereof. As the speed of ADCs continues to grow, the design of the S/H circuit becomes more challenging, and various solutions have been proposed to improve the speed of such S/H circuits. One prior art circuit solution for improving the speed of a S/H circuit is illustrated in prior art FIG.
3
and designated at reference numeral
30
. The S/H circuit
30
consists of four S/H subcircuits
32
a
-
32
d
coupled together in parallel. Each of the S/H subcircuits
32
a
-
32
d
operates individually as a S/H circuit, wherein the input V
IN
is passed to the output V
OUT
during a “sampling mode” and the state of the input is maintained on the output in the “hold mode”, respectively.
The speed of the S/H circuit
30
of
FIG. 3
is increased by using several individual S/H subcircuits interleaved in time. An exemplary sample timing diagram for the S/H circuit
30
is illustrated in prior art FIG.
4
. Note that with multiple S/H subcircuits interleaved in time, each subcircuit transitions through one sample and hold cycle in four clock (CLK) cycles, whereas if a similar speed were desired with only a single S/H subcircuit, the sample and hold functions each would have to be completed within a one-half (½) clock cycle. Therefore in the above parallel configuration, the overall speed is increased without requiring higher performance from the individual S/H subcircuit elements.
Referring again to prior art
FIG. 3
, although the pass gates at the output of the overall S/H circuit
30
might seem like a possible speed limitation, usually such S/H circuits are followed by one or more output buffers. In such a case, the RC filter of the pass gate and the input capacitance of the output buffer is usually fairly small compared with the speed gained through parallelism.
One problem with the technique provided by the circuit
30
of prior art
FIG. 3
is that if the S/H subcircuits
32
a
-
32
d
are not perfectly matched, then errors can occur. The three chief types of mismatch associated with the S/H circuit
30
are offset mismatch, gain mismatch and timing mismatch. A brief discussion of the operation of an individual conventional S/H subcircuit is provided below in order to appreciate the impact that timing mismatch has on the performance of the S/H circuits
30
.
An exemplary prior art sample and hold subcircuit is illustrated in prior art
FIG. 5
, and designated at reference numeral
40
. Circuit
40
is a detailed circuit of structure
32
a
in FIG.
3
. Transistor M
1
operates as a sampling switch, and C
HOLD
acts as a sampling capacitor. In the sampling mode, a sampling signal “S” is asserted, thereby closing a switch
42
, which activates M
1
(turns M
1
on). With M
1
on, V
IN
is passed to the output V
OUT
.
A significant time point relating to timing mismatch in S/H circuits deals with the instant when the sampling switch M
1
is deactivated, or turned off. Any deviation of the deactivation of M
1
from perfect CLK/N time periods will cause a timing mismatch between the various subcircuits and result in distortion at the output V
OUT
. To deactivate M
1
, the sample signal “S” goes low and a hold signal “H” is asserted, which causes a switch
43
to close. This instance pulls the gate of M
1
down to ground, thus turning M
1
off. Each S/H subcircuit has its own hold signal “H”; consequently, a primary source of the timing mismatch relates to mismatches in the switch M
1
driven by “H” and the arrival of the hold signal “H” at each subcircuit switch, respectively. In addition, even if no timing mismatch occurs between “H” signals of various subcircuits
32
a
-
32
d
, a sizing mismatch of switch
43
or M
1
between various subcircuits may exist which may contribute disadvantageously to timing mismatch.
There is a need in the art for a circuit and method for increasing the speed in sample and hold circuits in which timing mismatch is reduced substantially.
SUMMARY OF THE INVENTION
According to the present invention, a system and method of reducing timing mismatch in high speed S/H circuits is disclosed.
According to the present invention, timing mismatch related to the sampling switch in various S/H subcircuits is reduced by calibrating the subcircuits so that the hold signal of the subcircuits are modified so as to minimize timing mismatch between S/H subcircuits. In the above manner, the timing mismatch between the various S/H subcircuits associated with the arrival of the hold signal at its switch in each subcircuit is reduced substantially or eliminated altogether.
According to one aspect of the present invention, subcircuits within a parallel S/H circuit are calibrated so as to reduce timing mismatch by feeding a sinusoidal test signal into the analog input of a S/H circuit input and analyzing the circuit output. For example, the analog, generally sinusoidal output is converted to digital data and processed, for example, using a fast Fourier transform (FFT). The processed data, for example, an energy spectrum, is then analyzed and utilized to calibrate one or more of the S/H subcircuits by modifying the hold signal such that a timing mismatch between the S/H subcircuits is reduced substantially or eliminated altogether.
According to another aspect of the present invention, a high speed S/H circuit comprises a plurality of S/H subcircuits coupled together in parallel, a calibration circuit and a memory associated therewith. The calibration circuit is operable to modify a hold signal for each of the S/H subcircuits. In an exemplary illustration of the present invention, the calibration circuit operates to modify the hold signal of one or more S/H subcircuits so as to minimize an energy amplitude at one or more predetermined frequencies, thereby reducing distortion associated with timing mismatch. Based on the processing and analysis of the S/H circuit output, control data necessary to modify the hold (“H”) signal for the one or more of the S/H subcircuits is identified and saved in the memory. Subsequently, the calibration circuit may access the memory and utilize the control data to modify the hold signal for one or more of the S/H subcircuits and thereby reduce timing mismatch.
According to still another aspect of the present invention, a method for reducing timing mismatch in a S/H circuit is provided. The method comprises modifying the hold signal for one or more of a plurality of S/H subcircuits. The modified hold signals are then employed within the respective S/H subcircuits to thereby reduce the timing mismatch therebetween, thus reducing output distortion. In an exemplary illustration of the present in
Martin David A.
Spaeth Mark C.
Brady III W. James
Moore J. Dennis
Nguyen Khai
Telecky , Jr. Frederick J.
Texas Instruments Incorporated
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