Variable resistance circuit, operational amplification...

Radiant energy – Photocells; circuits and apparatus – Photocell controlled circuit

Reexamination Certificate

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Details

C250S2140RC, C250S2140LS

Reexamination Certificate

active

06403943

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a variable resistance circuit varying the resistance value thereof by turning on/off a plurality of switches connected in parallel with a plurality of serially connected resistors respectively, an operational amplification circuit employing this variable resistance circuit, a semiconductor integrated circuit employing this operational amplification circuit, a time constant switching circuit, and a waveform shaping circuit, having a small number of time constant errors, using this time constant switching circuit.
2. Description of the Prior Art
In recent years, optical disk drives such as a CD (compact disk) drive, a CD-ROM (compact disk read only memory) drive and the like come into wide use, followed by development of various semiconductor integrated circuits applied to these optical disk drives.
FIG. 14
is a block diagram showing the structure of a conventional semiconductor integrated circuit applied to a CD-ROM drive.
The circuit shown in
FIG. 14
, formed by a plurality of semiconductor integrated circuits, comprises a signal processing circuit
200
, an RF (radio frequency) amplifier
220
, a drive circuit
230
, a microcomputer
240
and a DRAM (dynamic random access memory)
250
.
The signal processing circuit
200
includes a DSP (digital signal processor)
201
, aDAC (digital-to-analog converter)
202
, a servo circuit
203
and an error correction circuit
204
. The RF amplifier
220
is formed by a bipolar integrated circuit with different components, and the signal processing circuit
200
is integrated into a single chip by a CMOS (complementary metal oxide semiconductor) integrated circuit.
An optical pickup
210
converts data recorded on a CD-ROM disk to an RF signal, and outputs the RF signal to the RF amplifier
220
. The RF amplifier
220
generates a reproduced signal (EFM (eight to fourteen modulation) signal), a focus error signal and a tracking error signal etc., and outputs these signals to the signal processing circuit
200
.
The signal processing circuit
200
creates a control signal for controlling the optical pickup
210
from the focus error signal, the tracking error signal etc. through the DSP
201
and the servo circuit
203
, and outputs the control signal to the drive circuit
230
. The drive circuit
230
drives an actuator provided in the optical pickup
210
in response to the input control signal, for controlling the optical pickup
210
to reproduce an excellent RF signal.
The signal processing circuit
200
further performs error correction of the reproduced data by the error correction circuit
204
with the DRAM
250
, for converting the reproduced data to an analog signal by the DAC
202
and outputting the analog signal when reproducing a sound signal.
The microcomputer
240
serves as a system controller controlling operations of the overall drive and transmits/receives data etc. to/from the signal processing circuit
200
at need so that the CD-ROM drive executes various operations.
The RF amplifier
220
of the CD-ROM drive having the aforementioned structure internally varies the amplification factor for the RF signal with various levels of RF signals for reproducing data from various optical disks such as a CD, a CD-ROM, a CD-RW (compact disk rewritable) and the like. Therefore, the RF amplifier
220
comprises a PGA (programmable gain amplifier) or the like varying the amplification factor for the RF signal, and employs a variable resistance circuit settable to various resistance values for gain control.
FIG. 15
is a circuit diagram showing the structure of a conventional variable resistance circuit. The variable resistance circuit shown in
FIG. 15
includes a decoding circuit
300
, switches SW
0
to SW
255
and resistors TR
0
to TR
255
.
The 256 resistors TR
0
to TR
255
are serially connected with each other, the resistance values of all resistors TR
0
to TR
255
are set to R (&OHgr;), and the resistors TR
0
to TR
255
are identical to each other. The switches SW
0
to SW
255
, connected in parallel with the corresponding ones of the resistors TR
0
to TR
255
respectively, are identical to each other. When the switches SW
0
to SW
255
are turned on, the resistors TR
0
to TR
255
connected therewith are so bypassed as to change the resistance value of the variable resistance circuit.
Control signals d
1
to d
8
of eight bits are input in the decoding circuit
300
. The control signal d
1
expresses the least significant bit, the control signal d
8
expresses the most significant bit, and the respective values of 0 to 255 can be expressed by the control signals d
1
to d
8
. The decoding circuit
300
decodes the control signals d
1
to d
8
of eight bits and outputs control signals for turning on/off the switches SW
0
to SW
255
and setting resistance values corresponding to data expressed by the control signals d
1
to d
8
of eight bits to the switches SW
0
to SW
255
.
The switches SW
0
to SW
255
are turned on/off by the control signals output from the decoding circuit
300
respectively, and the ON-state switches bypass the resistors. Therefore, the resistance value of the variable resistance circuit is set to an arbitrary value among 0 (&OHgr;), R (&OHgr;), 2R (&OHgr;), . . . , 255R (&OHgr;) by bypassing an arbitrary resistor among the
256
resistors TR
0
to TR
255
in response to the control signals d
1
to d
8
of eight bits.
FIG. 16
is a circuit diagram showing the structure of another conventional variable resistance circuit. The variable resistance circuit shown in
FIG. 16
includes switches SW
10
to SW
17
and resistors TR
10
to TR
17
. The eight resistors TR
10
to TR
17
are serially connected with each other. The resistors TR
10
, TR
11
and TR
12
have resistance values R (&OHgr;), 2R (&OHgr;) and 4R (&OHgr;) respectively, and the resistance values of the subsequent resistors TR
13
to TR
17
are successively doubled so that the resistance value of the final resistor TR
17
is set to 128 R (&OHgr;).
The switches SW
10
to SW
17
are connected in parallel with the corresponding ones of the resistors TR
10
to TR
17
respectively, and turned on/off thereby bypassing the resistors TR
10
to TR
17
connected therewith.
The aforementioned control signals d
1
to d
8
of eight bits are input in the switches SW
10
to SW
17
respectively, for setting the resistance value of the variable resistance circuit to an arbitrary value among 0 (&OHgr;), 2R (&OHgr;), . . . , 255R (&OHgr;).
As hereinabove described, the variable resistance circuit shown in
FIG. 15
requires the
256
resistors TR
0
to TR
255
and the
256
switches SW
0
to SW
255
as well as the decoding circuit
300
decoding the control signals d
1
to d
8
of eight bits, in order to implement resolution of eight bits. Therefore, the circuit area of the variable resistance circuit is remarkably increased. When such a variable resistance circuit having a large circuit area is integrated with other circuits, the area of the integrated circuit is disadvantageously increased.
Further, linearity of the resistance value of the variable resistance circuit shown in
FIG. 16
is deteriorated due to parasitic resistances of the switches SW
10
to SW
17
. Assuming that the parasitic resistance value of each of the switches SW
10
to SW
17
is r (&OHgr;), the resistance value of the variable resistance circuit is 255R (&OHgr;) when all switches SW
0
to SW
17
are off, 254R+r×R/(r+R) (&OHgr;) when the switch SW
10
is on and the switches SW
11
to SW
17
are off, 253R+2r×R/(r+2R) (&OHgr;) when the switch SW
11
is on and the switches SW
10
and SW
12
to SW
17
are off, or 252R+r×R/(r+R)+2r×R/(r+2R) (&OHgr;) when the switches SW
10
and SW
11
are on and the switches SW
12
to SW
17
are off.
Thus, the change rate of the resistance value of the variable resistance circuit is R−r×R/(r+R) (&OHgr;), R+r×R/(r+R)−2r×R/(r+2R) (&OHgr;) or R−r×R

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