Silicon carbide barc in dual damascene processing

Details Silicon carbide barc in dual damascene processing Silicon carbide barc in dual damascene processing

2001-02-07

2002-10-15

Quach, T. N. (Department: 2814)

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Of specified material other than unalloyed aluminum

C257S762000, C438S624000, C438S636000

Reexamination Certificate

active

06465889

ABSTRACT:

TECHNICAL FIELD
The present invention relates to semiconductor devices having accurately dimensioned interconnection patterns. The present invention is particularly applicable to ultra large-scale integrated (ULSI) circuit devices having features in the deep sub-micron regime.
BACKGROUND ART
As integrated circuit geometries continue to plunge into the deep sub-micron regime, the requirements for dimensional accuracy becomes increasingly difficult to satisfy. Integration technology is considered one of the most demanding aspects of fabricating ULSI devices. Demands for ULSI semiconductor wiring require increasingly denser arrays with minimal spacings between narrower conductive lines. Implementation becomes problematic in manufacturing semiconductor devices having a design rule of about 0.12 micron and under.
Conventional semiconductor devices comprise a semiconductor substrate, typically doped monocrystalline silicon, and a plurality of sequentially formed interlayer dielectrics and conductive patterns. An integrated circuit is formed containing a plurality of conductive patterns comprising conductive lines separated by interwiring spacings, and a plurality of interconnect lines, such as bus lines, bit lines, word lines and logic interconnect lines. Typically, the conductive patterns on different levels, i.e., upper and lower levels, are electrically connected by a conductive plug filling a via hole, while a conductive plug filling a contact hole establishes electrical contact with an active region on a semiconductor substrate, such as a source/drain region. Conductive lines are formed in trenches which typically extend substantially horizontal with respect to the semiconductor substrate. Semiconductor “chips” comprising five or more levels of metallization are becoming more prevalent as feature sizes shrink into the deep sub-micron regime.
It A conductive plug filling a via hole is typically formed by depositing an interlayer dielectric (ILD) on a conductive layer comprising at least one conductive feature, forming an opening through the ILD by conventional photolithographic and etching techniques, and filling the opening with a conductive material. Excess conductive material or the overburden on the surface of the ILD is typically removed by chemical-mechanical polishing (CMP). One such method is known as damascene and basically involves forming an opening in the ILD and filling the opening with a metal. Dual damascene techniques involve forming an opening comprising a lower contact hole or via hole section in communication with an upper trench section, which opening is filled with a conductive material, typically a metal, to simultaneously form a conductive plug in electrical contact with a conductive line.
Copper (Cu) and Cu alloys have received considerable attention as alternative metallurgy to aluminum (Al) in interconnect metallizations. Cu is relatively inexpensive, easy to process, and has a lower resistively than Al. In addition, Cu has improved electrical properties vis-à-vis tungsten (W), making Cu a desirable metal for use as a conductive plug as well as conductive wiring. However, due to Cu diffusion through dielectric materials, such as silicon dioxide, Cu interconnect structures must be encapsulated by a diffusion barrier layer. Typical diffusion barrier materials include tantalum (Ta), tantalum nitride (TaN), titanium (Ti), titanium nitride (TiN), titanium-tungsten (TiW), Tungsten (W), tungsten nitride (WN), Ti-TiN, titanium silicon nitride (TiSiN), tungsten silicon nitride (WSiN), tantalum silicon nitride (TaSiN) and silicon nitride for encapsulating Cu. The use of such barrier materials to encapsulate Cu is not limited to the interface between Cu and the ILD, but includes interfaces with other metals as well.
Cu interconnect technology, by and large, has been implemented employing damascene techniques, wherein a first dielectric layer, such as a silicon oxide layer, e.g., derived from tetraethyl orthosilicate (TEOS) or silane, or a low dielectric constant material, i.e., a material having a dielectric constant of no greater than about 3.9 (with a dielectric constant of 1 representing a vacuum), is formed lover an underlying metal level having a capping layer thereon, e.g., a Cu or Cu alloy features with a silicon nitride capping layer. A barrier layer and optional seedlayer are then deposited, followed by Cu deposition, as by electrodeposition or electroless deposition.
In implementing dual damascene techniques, particularly via first-trench last dual damascene processing, on a silicon nitride capped lower Cu or Cu alloy feature, it was found difficult to form the overlying trench with a high degree of dimensional accuracy. It was also found that such dual damascene processing required a large number of manipulative steps, thereby reducing efficiency and increasing manufacturing costs.
In implementing conventional damascene techniques, for example as schematically illustrated in
FIGS. 1 through 3
, an underlying metal feature
16
, e.g., a Cu or Cu alloy line, is formed in an underlying dielectric layer
10
with a silicon nitride capping layer
11
formed thereon. Silicon nitride capping layer
11
does not exhibit favorable anti-reflective properties to enable subsequent photolithographic processing with high dimensional accuracy, particularly as dimensions plunge into the deep sub-micron regime. Silicon oxynitride is not a viable candidate for capping layer
11
, since silicon oxynitride would not effectively prevent Cu diffusion.
As further illustrated in
FIG. 1
, a first dielectric layer
12
is formed over underlying dielectric layer
10
on capping layer
11
, a middle etch stop layer
13
, such as silicon oxynitride, is formed on dielectric layer
12
, and a second dielectric layer
14
is formed on middle etch stop layer
13
. A photoresist mask (not shown) is then formed on second dielectric layer
14
and anisotropic etching is conducted to form via hole
15
extending through second dielectric layer
14
, middle etch stop layer
13
and first dielectric layer
12
. A thin organic bottom anti-reflective coating (BARC)
17
is then optionally formed at the bottom of via hole
15
.
A second photoresist mask
18
is then formed over second dielectric layer
14
. Second photoresist mask
18
typically has a thickness “T” of about 4,000 Å to about 6,000 Å and contains an opening “W” substantially corresponding to the width of the trench to be formed in second dielectric layer
14
.
Adverting to
FIG. 3
, anisotropic etching is then conducted to form a trench
20
in second dielectric layer
14
stopping on middle etch stop layer
13
which is selected for its high etch selectivity with respect to second dielectric layer
14
. Optional organic BARC
17
is removed during or subsequent to trench formation. In implementing Cu or Cu alloy metallization, a barrier layer
30
, such as Ta or TaN, is deposited to line the dual damascene opening comprising upper trench
20
communicating with lower via hole
12
, and a seedlayer
31
deposited thereon. A Cu or Cu alloy is then deposited by electrodeposition or electroless deposition to fill the dual damascene opening. The over-burden is then removed by chemical-mechanical polishing (CMP) such that the upper surface
24
of the filled damascene opening is substantially coplanar with the upper surface
25
of the second dielectric layer
14
. A capping layer
26
, such as silicon nitride, is then deposited to encapsulate the dual damascene structure comprising Cu or Cu alloy line
22
connected to Cu or Cu alloy via
23
which is electrically connected to underlying Cu or Cu alloy line
16
.
As miniaturization proceeds apace with an attendant shrinkage in the size of metal lines, e.g., metal lines having a width of about 0.3 micron and under, e.g., about 0.2 micron and under, it becomes increasingly difficult to maintain the requisite dimensional accuracy of the metal lines, particularly when implementing dual damascene techniques. In addition, the implementation of dual damascene techniques in Cu

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