Pulse or digital communications – Bandwidth reduction or expansion – Television or motion video signal
Reexamination Certificate
2000-12-15
2002-02-12
Diep, Nhon T (Department: 2613)
Pulse or digital communications
Bandwidth reduction or expansion
Television or motion video signal
Reexamination Certificate
active
06347119
ABSTRACT:
TECHNICAL FIELD
This invention relates to a communication apparatus, a communication method and a storage medium. More particularly, it relates to a communication apparatus, a communication method and a storage medium for transmitting and receiving digital audio data and video data, utilizing ATM communication technique.
BACKGROUND ART
FIG. 1
illustrates the structure of a conventional data communication system. The network
3
that connects the encoding side and the decoding side is assumed to be using a satellite as in the transmission method employed in digital CS broadcasting. In other words, it is assumed that the data transmitted via the network
3
is delayed at regular intervals.
The encoder
1
encodes, for example, video data and audio data, as the data to be transmitted, in accordance with the MPEG-2 system and outputs the encoded data to the system encoder
2
. The system encoder
2
encodes the input video and audio data, generating a transport stream packet. If necessary, the system encoder
2
multiplexes the transport stream packet with another transport stream packet and outputs them onto the network
3
.
The system encoder
2
incorporates PCR (Program Clock Reference), i.e., a time stamp, into the header of the transport stream packet generated, as is shown in FIG.
2
. (Hereinafter, the transport stream packet into which the PCR has been incorporated shall be called “PCR packet”.) The PCR is a count value of the system clock C
1
(a clock having frequency of 27 MHz in the case of the MPEG-2 system) which has been counted at the timing of outputting the transport stream from the encoding side. The PCR is incorporated into the transport stream so that at least one may be output within 0.1 second from the encoding side in accordance with the MPEG-2 system standards.
Referring back to
FIG. 1
, the transport stream packet (including the PCR packet) is transmitted through the network
3
, reaches the decoding side and input to the system decoder
4
provided in the decoding side. The data transmitted via the network
3
is delayed by a predetermined time. The PCR (PCR packet) therefore reaches the decoding side in the same interval as the interval at which it has been transmitted from the encoding side. (The difference should fall within +/−500 ns.)
The system decoder
4
de-packetizes the input transport stream packet, generating an audio stream or a video stream, which is output to the decoder
5
. The system decoder
4
extracts the PCR from the PCR packet as is illustrated in FIG.
2
. The decoder
4
compares the PCR with the count value of the system clock C
2
(a clock signal having frequency of 27 MHz) in the decoding side, which has been obtained at the timing of extracting the PCR. The decoder
4
adjusts the speed of the system clock C
2
based on the results of comparison, and supplies the system clock C
2
to the decoder
5
.
The decoder
5
decodes the audio data or video data supplied from the system decoder
4
, in synchronism with the system clock C
2
supplied from the system decoder
4
.
How the system clock C
2
is generated (adjusted) in the decoding side will be now be described, with reference to
FIGS. 3 and 4
. The system decoder
4
has the structure shown in FIG.
3
. The transport stream packet supplied to the system decoder
4
is supplied to the system decoder
11
and time stamp extracting circuit
12
of the system decoder
4
.
As shown in
FIG. 2
, the time stamp extracting circuit
12
extracts the PCR incorporated in the PCR packet and supplies the PCR to a PLL circuit
13
. The PLL circuit
13
has, for example, the structure shown in FIG.
4
. It has a subtracter
21
, to which the PCR extracted by the time stamp extracting circuit is input. Also input to the subtracter
21
is the count value of a counter
24
when the PCR is input. The count value is a count of the number of clock pulses output from a VCO (Voltage-Controlled Oscillator)
23
. The subtracter
21
finds the difference between the PCR and the count value, which have been supplied from the time stamp extracting circuit
12
and the counter
24
, respectively. A low-pass filter (hereinafter referred to as “LPF”)
22
smoothes, with time, the result of the subtraction supplied from the subtracter
21
and outputs the same to the VCO
23
. The VCO
23
, which also functions as a D/A converter, then converts the digital signal input from the LPF
22
to an analog signal. Using the analog signal as a control voltage, the VCO generates a system clock C
2
having a frequency corresponding to the control voltage. The VCO
23
then outputs the system clock to the counter
24
and the decoder
5
.
The counter
24
counts the pulses of the system clock C
2
supplied from the VCO
23
acting as a D/A converter. The count value of the counter
24
is supplied to the substracter
21
as the signal that indicates the frequency and phase that the system clock C
2
has at this time. That is, the PLL circuit
13
adjust the speed of the system clock C
2
so that the difference between the PCR value incorporated in the transport stream packet and the count value of the system clock C
2
, obtained when the PCR was extracted (when the PCR packet reaches the decoding side) may be eliminated. As a result, the system clock C
2
in the decoding side becomes synchronous with the system clock C
1
in the encoding side.
With reference to
FIG. 3
again, the system decoder
11
de-packetizes the input transport stream packet, generating an audio stream and a video stream. The audio stream and video stream are output to the decoder
5
.
A satellite may be used as the network
3
as in the transmission method employed in satellite broadcasting. In this case, a fixed delay is added to the transport stream packet transmitted from the encoding side. That is, the transport stream packet transmitted from the encoding side reaches the decoding side, earlier or later by a specific time. Since the specific time is constant, the interval at which the transport stream packet (including the PCR packet) reaches the decoding side is the same as the interval at which it is output from the encoding side. Thus, the system clock C
2
in the decoding side is generated, synchronous with the system clock Cl in the encoding side, by the method explained with reference to
FIGS. 3 and 4
.
If the network
3
is an ATM (Asynchronous Transfer Mode) network, however, the transport stream packet transmitted from the encoding side is delayed, not at a constant interval but at an interval fluctuating in the range of 1 ms to 2 ms (hereinafter referred to as “delay fluctuation”) . The delay fluctuation cannot be absorbed in the data transmission system described above. After all, the delay greatly exceeds the MPEG-2 standard range of +/−500 ns. In consequence, the data cannot be reproduced adequately.
A synchronization method, such as adaptive clock method, has been proposed. In the method, the delay fluctuation is first attenuated to some extent and a system clock is then generated.
FIG. 5
shows an example of the adaptive clock circuit
51
which is provided in the decoding side and which uses the adaptive clock method. It is assumed here that delay fluctuation exists in the data transmitted via a network
50
.
The data with delay fluctuation, transmitted via the network
50
, is input to the FIFO
52
incorporated in the adaptive clock circuit
51
. The FIFO
52
holes the data for some time and outputs the data in response to a read clock supplied from a control circuit
53
. The FIFO
52
outputs a signal to an LPF
54
. The signal represents the data occupation ratio of the FIFO
52
. The LPF
54
smoothes the data occupation ratio and outputs the same to the control circuit
53
.
The control circuit
53
controls the speed of a read clock to be output to the FIFO
52
, so that the data supplied from the LPF
54
(i.e., the smoothed data occupation ratio of the FIFO
52
) may have a prescribed value. That is, the clock controlled by the control circuit
53
is used as system clock in the deco
Itakura Eisaburo
Matsumura Youichi
Seto Hiroaki
Tahara Katsumi
Diep Nhon T
Frommer William S.
Frommer & Lawrence & Haug LLP
Simon Darren M.
Sony Corporation
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