Shift register

Details Shift register Shift register

2000-11-06

2002-02-05

Wambach, Margaret R. (Department: 2816)

Electrical pulse counters, pulse dividers, or shift registers: c

Systems

Using shift register

C377S075000

Reexamination Certificate

active

06345085

ABSTRACT:

This application claims the benefit of Korean Patent Application No. 1999-48738, filed on Nov. 5, 1999, which is hereby incorporated by reference for all purposes as if fully set forth herein.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a driving circuit for an active matrix display, and more particularly to a shift register for driving a pixel array that is adapted to prevent a short of a capacitor.
2. Discussion of the Related Art
Generally, a liquid crystal display (LCD) with an active matrix driving system uses thin film transistors (TFTs) as a switching device to display a natural moving picture. Such an LCD has been widely used for a monitor for a personal computer or a notebook computer as well as office automation equipment such as copying machines, etc., and portable equipment such as cellular phones and pagers, etc.
The active matrix LCD includes a gate driving circuit for sequentially applying a scanning pulse to row lines connected to gate electrodes of TFTs to sequentially scan a pixel train for each row line. This gate driving circuit consists of a plurality of shift registers connected in cascade to sequentially generate a scanning pulse in response to a start pulse.
Referring to
FIG. 1
, the conventional shift register includes n stages
2
1
to
2
n
connected to a start pulse input line. Output lines
4
1
to
4
n
of the n stages
2
1
to
2
n
are connected to n row lines ROW
1
to ROWn included in a pixel array, respectively. A scanning pulse SP is applied to the first stage
2
1
, and output signals g
1
to g
n−1
of the first to (n−1)th stages are applied to the respective subsequent stages as scanning pulses. The input signals of the shift register, that is, the scanning pulse, first to fourth clock signals C
1
to C
4
having a phase delayed sequentially, the supply voltage VDD and the ground voltage VSS, are applied from external sources. As shown in
FIG. 2
, each of the stages
2
1
to
2
n
includes: a first NMOS transistor T
1
connected between a first node P
1
and a fourth node P
4
; a second NMOS transistor T
2
connected between the first node P
1
, a second node P
2
and a ground voltage line
10
; a third NMOS transistor T
3
connected between a supply voltage line
8
, a third clock signal line
6
c
and the second node P
2
; a fourth NMOS transistor T
4
connected between the second node P
2
, the fourth node P
4
, and the ground voltage line
10
; a first capacitor CP
1
connected between the first node P
1
and an output line
4
i
; a fifth NMOS transistor T
5
connected between the first clock signal line
6
a
and the output line
4
i
; and a sixth NMOS transistor T
6
connected between the second node P
2
, the output line
4
i
and the ground voltage line
10
.
When the (i−1)th row line input signal g
i−1
having a high level is applied from the previous stage
2
i−1
, the first and fourth NMOS transistors T
1
and T
4
are turned on. Then, a voltage at the first node P
1
goes to a high level by the supply voltage VDD applied upon turning-on of the first NMOS transistor T
1
, whereas a voltage at the second node P
2
is discharged to the ground voltage line
10
upon turning-on of the fourth NMOS transistor T
4
, so as to have a low level. As can be seen from
FIG. 3
, the third clock signal C
3
remains at a low level voltage in a time interval when the (i−1)th row line input signal g
i−1
has a high level voltage. In other words, a high-level voltage region of the third clock signal C
3
does not overlap with that of (i−1)th row line input signal g
i−1
. Thus, the third and fourth NMOS transistors T
3
and T
4
are not turned on at the same time, so that a voltage at the second node P
2
is determined independently of a channel width ratio (or resistance ratio) of the third NMOS transistor T
3
to the fourth NMOS transistor T
4
. Accordingly, even though element characteristics of the third and fourth NMOS transistors T
3
and T
4
are non-uniform, a circuit characteristic of the shift register is not changed to such a large extent that a normal operation is impossible. Also, since the third and fourth NMOS transistors T
3
and T
4
are not turned on at the same time, an overcurrent does not flow in the third and fourth NMOS transistors T
3
and T
4
. As a result, not only are the element characteristics of the third and fourth NMOS transistors T
3
and T
4
not deteriorated, but also the power consumption is reduced.
If a high level voltage emerges at the first node P
1
, then the fifth NMOS transistor T
5
is turned on. In this state, the output line
4
i
begins to discharge the first clock signal C
1
passing through the source and drain of the fifth NMOS transistor T
5
when the first clock signal C
1
has a high level voltage. Thus, a high level voltage emerges at the output line
4
i
. When a high level voltage of first clock signal C
1
is applied to the output line
4
i
, the capacitor CP
1
raises a voltage at the first node P
1
by the voltage level of the first clock signal C
1
. As the gate voltage is increased by the capacitor CP
1
, the fifth NMOS transistor T
5
delivers the high-level first clock signal C
1
into the output line
4
i
rapidly without any attenuation. Accordingly, a voltage loss caused by a threshold voltage of the fifth NMOS transistor T
5
is minimized.
Subsequently, if the first clock signal C
1
is changed from a high level voltage to a low level voltage, then an output voltage Vout at the output line
4
i
also is changed from a high level voltage to a low level voltage. This results from the fifth NMOS transistor T
5
being in a turned-on state due to a voltage at the first node P
1
.
Next, if the third clock signal C
3
is changed from a low level voltage to a high level voltage, then the third NMOS transistor T
3
is turned on and hence a voltage at the second node P
2
has a high level. The second NMOS transistor T
2
also is turned on by virtue of a high level voltage at the second node P
2
applied to its gate to discharge a voltage at the first node P
1
into a ground voltage source VSS connected to the ground voltage line
10
. Likewise, the sixth NMOS transistor T
6
also discharges a voltage at the output line
4
i
, via the ground voltage line
10
, into the ground voltage source VSS by virtue of a high level voltage at the second node P
2
applied to its gate. As a result, a voltage at the first node P
1
and then output voltage at the output line
4
i
have a low level.
Meanwhile, when the first clock signal C
1
input to the drain of the fifth NMOS transistor T
5
changes from a low level voltage to a high level voltage in such a state that a voltage at the first node P
1
remains at a high level, the voltage at the first node P
1
rises. In this case, a voltage rise width )Vp at the first node P
1
can be set accurately by the first capacitor CP
1
connected between the first node P
1
and the output node
4
i
and a capacitor CP
12
provided between the first node P
1
and the ground voltage line
10
. The voltage rise width )Vp at the first node P
1
is given by the following equation:
Δ
⁢
 
⁢
Vp
=
CP1
+
C
OX
CP12
+
CP1
+
C
OX
⁢
Δ
⁢
 
⁢
Vout
(
1
)
wherein C
ox
represents a parasitic capacitance of the fifth NMOS transistor T
5
. Capacitance values of the capacitors CP
1
and CP
12
can be set to about 0.1 to 10 pF.
The capacitor CP
2
connected between the second node P
2
and the ground voltage line
10
restrains a voltage variation at the second node P
2
when the output voltage Vout at the output node
4
i
changes and, at the same time, restrains a voltage variation at the second node P
2
caused by a leakage current from the NMOS transistors.
Since the capacitors CP
1
, CP
2
and CP
12
are used for the purpose of reducing a voltage drop caused by an element leakage current and a voltage variation at the first and second nodes P
1
and P
2
caused by a coupling effect, the shift resister does not malfunction even when the capacitors

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