Semiconductor memory employing charge-coupled shift registers wi

Details Semiconductor memory employing charge-coupled shift registers wi Semiconductor memory employing charge-coupled shift registers wi

1974-12-06

1976-03-16

Hecker, Stuart N.

Communications: electrical

Digital comparator systems

307221D, 340173DR, 357 24, G11C 1928, G11C 2100, G11C 700

Patent

active

039449904

ABSTRACT:
A serial memory employing a plurality of charge-coupled shift registers fabricated with MOS technology and using double layer polycrystalline silicon gates. Each shift register includes two pairs of parallel channels; charge flows in opposite directions in each pair of channels. Multiplexing is utilized to refresh charge between each pair of channels through two refreshing amplifiers, one disposed at each end of the channels. The topographical efficiency of the design permits fabrication of a dense memory.

REFERENCES:
patent: 3760202 (1973-09-01), Kosonocky

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