Delay circuit having low operating environment dependency

Details Delay circuit having low operating environment dependency Delay circuit having low operating environment dependency

2000-12-14

2002-06-11

Tran, Toan (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Having specific delay in producing output waveform

C327S264000

Reexamination Certificate

active

06404258

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a delay circuit, and more specifically, to a delay circuit that has a low dependence on the operating environment such as a power-supply voltage and an operating temperature.
2. Description of the Background Art
In a semiconductor device, delay circuits are used in various portions in order to delay the signals by prescribed period of time. A delay circuit is used for such purpose as adjusting the timing of a signal. For instance, a delay circuit is used as follows in a processing system including a clock synchronous semiconductor memory device that performs signal/data transfer in synchronization with a clock signal. Normally, in a processing system, the distance between a processor (or a memory controller) and the respective clock synchronous semiconductor memory devices varies from device to device. If the clock signal is a common clock signal such as a system clock, the timing, relative to the clock signal, at which a signal/data from a semiconductor memory device arrives at the processor varies depending on the distance between each semiconductor memory device and the processor (or the memory controller). In order to match the arrival timing of the signal/data relative to the clock signal throughout all the semiconductor memory devices by compensating for the time difference in the arrival timing, a delay circuit such as one called vernier is employed within the semiconductor memory devices. Using this vernier, the output timings of the signal/data is adjusted so as to match the timings of the signal arrival at the processor (or the memory controller) among semiconductor memory devices.
FIG. 55
is a diagram representing an example of the arrangement of a conventional delay circuit. In
FIG. 55
, the delay circuit includes an inverter circuit
900
for inverting an input signal IN and transmitting the inverted signal onto an internal node
901
, an inverter circuit
903
for inverting the signal on node
901
to produce an output signal OUT, and a capacitance element
902
connected between node
901
and a ground node.
Inverter circuits
900
and
903
have an identical CMOS arrangement, and the arrangement of inverter circuit
900
is representatively shown in FIG.
55
. Inverter circuit
900
includes a P-channel MOS transistor (insulated gate type field effect transistor) PQ connected between a power-supply node and node
901
and receiving input signal IN at a gate, and an N-channel MOS transistor NQ connected between node
901
and a ground node and receiving input signal IN at a gate. These MOS transistors PQ and NQ have a resistance R when made conductive.
As shown in
FIG. 56
, when input signal IN is at a logic low or “L” level, node
901
is at a logic high or “H” level, and an electrode node, connected to node
901
, of capacitance element
902
is charged to the power-supply voltage level. At this time, output signal OUT is at the L level.
When input signal IN rises to the H level, P-channel MOS transistor PQ transitions to the off state, while N-channel MOS transistor NQ attains the on state so that the accumulated charges in node
901
are discharged through MOS transistor NQ. The discharging rate of node
901
is determined by the capacitance value C of capacitance element
902
and the on-resistance (channel resistance when made conductive) R of MOS transistor NQ. When the voltage level of node
901
exceeds the input logic threshold voltage of inverter
903
, output signal OUT rises from the L level to the H level.
On the other hand, when input signal IN falls from the H level to the L level, capacitance element
902
is charged via P-channel MOS transistor PQ. The rate at which the voltage level of node
901
rises is determined by the on-resistance R of MOS transistor PQ and capacitance value C of capacitance element
902
. When the voltage level of node
901
exceeds the input logic threshold voltage of inverter
903
, output signal OUT falls from the H level to the L level.
Thus, the time constant R·C determined by capacitance value C of capacitance element
902
and the on-resistances R of MOS transistors PQ and NQ determines the charging/discharging rate of node
901
, and the delay time &tgr; of output signal OUT relative to input signal IN is determined depending on the charging/discharging rate of node
901
.
In the arrangement of the delay circuit shown in
FIG. 55
, the delay time is determined by the on-resistances R of MOS transistors PQ and NQ and capacitance value C of capacitance element
902
. The on-resistances R of MOS transistors PQ and NQ, however, depend on the power-supply voltage Vcc. In other words, in the case of the N-channel MOS transistor NQ, although the on-resistance R is the smallest when its gate voltage is at power-supply voltage Vcc in operation, the on-resistance itself depends on its gate to source voltage (the channel inversion layer attains a deeper on state as the gate to source voltage becomes larger). On the other hand, in the case of the P-channel MOS transistor PQ, the on-resistance R is the smallest when input signal IN is at the L level (the ground voltage level) in operation. The on-resistance of P-channel MOS transistor PQ also is dependent on the gate to source voltage, and thus, is dependent on the power-supply voltage Vcc.
There is a permissible range of ±5%, for instance, for the power-supply voltage Vcc. When exact precision is not required for delay time &tgr;, this permissible range of the power-supply voltage does not cause a significant problem. The timing adjustment in a semiconductor device operating at a high speed, however, requires the precision on the order of ns (nano seconds) for delay time &tgr;. In this case, the dependency of delay time &tgr; on power-supply voltage Vcc cannot be neglected, and it becomes impossible to ensure the accurate internal operation even when the power-supply voltage Vcc is within its permissible range.
In addition, on-resistances R of MOS transistors PQ and NQ also depend on the operating temperature such that, in general, the on-resistances R becomes lower when the operating temperature rises.
Particularly, when the semiconductor device operates in synchronization with a clock signal as in the case of a clock synchronous semiconductor memory device, the internal timing must be matched accurately. The accurate internal operation, however, cannot be ensured if the delay time of the delay circuit fluctuates according to the fluctuation of the operating environment such as the power-supply voltage and the operating temperature.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a delay circuit that has a low dependence on the fluctuation of the operating environment.
Another object of the present invention is to provide a delay circuit with suppressed fluctuation of the delay time regardless of the fluctuation of the operating environment.
A still another object of the present invention is to provide a delay circuit of high precision that is used for the timing adjustment of internal signals such as an internal clock signal and an internal control signal in a clock synchronous semiconductor memory device.
According to a first aspect of the present invention, the delay circuit includes a drive circuit for driving an output node according to a first input signal. The voltage level of the output signal from this drive circuit changes between a first voltage level and a second voltage level.
According to the first aspect of the present invention, the delay circuit further includes a capacitance element, a delay control circuit coupled between the output node and the capacitance element for isolating the capacitance element from the output node when a signal on the output node is between a first voltage level and a prescribed voltage level between the first voltage level and a second voltage level and for coupling the capacitance element to the output node when the signal on the output node is between the prescribed voltage level and the second voltage l

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