Multilayer wiring board

Details Multilayer wiring board Multilayer wiring board

2000-07-13

2002-06-18

Talbott, David L. (Department: 2827)

Electricity: conductors and insulators

Conduits, cables or conductors

Preformed panel circuit arrangement

C174S255000, C174S262000, C174S264000, C361S792000, C361S794000, C361S803000

Reexamination Certificate

active

06407343

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to a multilayer wiring board which can carry a large number of LSI chips used for central processing units (CPUs) for large computers, the multilayer wiring board having via holes for supplying the power to the mounted LSIs.
Conventionally, multilayer printed wiring boards have been used for LSI chip mounted wiring boards. The multilayer printed wiring board is fabricated by alternately laminating a copper clad laminate acting as core materials and prepregs acting as an adhesive sheet and then thermally pressing the laminated structure as one piece body. In order to electrically interconnect laminated plates, after core materials and prepregs are integrally laminated, through holes are formed in the laminated structure with a drill. Then, the inner walls of the through holes are plated with copper. Usually, the multilayer printed wiring board is power supplied or grounded via the through holes.
Recently, multilayer wiring boards, in which polyimide resin acting as interlayer insulation is formed on a ceramic substrate, have been used for large computers demanding a high wiring density.
FIG. 14
is a cross-sectional view illustrating a conventional polyimide/ceramic multilayer wiring board.
A ceramic substrate
150
has through holes
151
therein each which electrically connects with an IO terminal
156
. Wiring layers are formed on the surface of the ceramic substrate
150
. Plural polyimide resin layers
152
, each in which a power-source via hole
112
is formed, are build-up on the ceramic substrate
150
.
Each polyimide resin layer
152
is made by repeating a series of steps including a polyimide-resin-layer forming step and a wiring layer forming step. The polyimide-resin-layer forming step includes the steps of coating a polyimide precursor on the ceramic substrate
150
, drying it, and then forming a power-source via hole
112
in the coated film. The wiring layer forming step includes a photolithographic process, vacuum deposition, and plating.
In such a layer structure, each of the
1
a
M layer, the
2
a
M layer, the
4
a
M layer, the
5
a
M layer, and the
7
a
M layer acts as a signal layer. Each of the
0
a
M layer, the
3
a
M layer, and the
6
a
M layer acts as the grounding layer. The
8
a
M layer acts as a cover surface layer. A power-source conductive pattern
100
a
with power-source via holes
112
is formed on each of the
8
a
M layer, the
7
a
M layer, the
4
am
layer, and the
1
a
M. Similarly, a power-source conductive pattern
100
b
is formed on each of the
6
a
M layer, the
3
a
M layer, and the
0
a
M layer. A power-source conductive pattern
100
c
is formed on each of the
5
a
M layer and the
2
a
M layer.
In order to energize the LSI
155
assembled on the upper surface of the polyimide/ceramic multilayer wiring board with the above-mentioned structure, the power is first guided from the IO terminal
156
formed on the back surface of the ceramic substrate
150
to the
0
a
M layer through via holes. Moreover, the power is supplied to the soldering bump
154
through the
0
a
M layer and through the power-source via hole
112
of each layer and through the pad
188
on the
8
a
M layer being a cover surface layer.
Another mounting pad (not shown) is electrically connected with another soldering bump of the LSI
155
so that the power is electrically connected to the signal layer and the ground layer.
FIG. 15
illustrates a copper-foiled power-source conductor pattern with power-source via holes, arranged on the polyimide/ceramic multilayer wiring board shown in FIG.
14
. Power-source via holes
112
are respectively formed at three points of nine points where line segments X
1a
, X
2a
and X
3a
dividing in the X direction of the power-source conductor pattern cross with line segments Y
1a
, Y
2a
and Y
3a
dividing in the Y-direction thereof. The power-source conductive pattern
100
is of the so-called 3×3 matrix type. Each power-source conductive pattern
112
is formed within the via hole land
113
through a photolithographic process.
The power-source conductive pattern
100
has, for example, a square of 189 (&mgr;m)×189 (&mgr;m). The via hole land
113
has a square of 56 (&mgr;m)×56 (&mgr;m). The power-source via hole
112
has rounded corners R and is of a square of 45 (&mgr;m)×45 (&mgr;m).
FIGS. 16A
to
16
I illustrate power-source conductive patterns arranged on each of laminated layers in the polyimide/ceramic multilayer wiring board shown in FIG.
14
. That is,
FIG. 16I
shows the bottom layer.
FIG. 16A
shows the top layer. The power-source conductive patterns
100
a
,
100
b
and
100
c
as well as the via holes
112
a
,
112
b
and
112
c
respectively therein are represented schematically.
FIG. 16A
shows the power-source conductive pattern
100
a
formed on the
8
a
M layer covering the surface of the top layer.
FIG. 16B
shows the power-source conductive pattern
100
a
arranged on the
7
a
M layer on which a signal line is formed in the Y-direction.
FIG. 16E
shows the power-source conductive pattern
100
a
arranged on the
4
a
M layer on which a signal line is formed in the Y-direction.
FIG. 16H
shows the power-source conductive pattern
100
a
arranged on the
1
a
M layer on which a signal line is formed in the Y-direction.
FIG. 16C
shows the power-source conductive pattern
100
b
arranged on the
6
a
M layer or the ground layer connected to the ground.
FIG. 16F
shows the power-source conductive pattern
100
b
arranged on the
3
a
M layer or the ground layer connected to the ground.
FIG. 16I
shows the power-source conductive pattern
100
b
arranged on the
0
a
M layer or the ground layer connected to the ground.
Moreover,
FIG. 16D
shows the power-source conductive pattern
100
c
arranged on the
5
a
M layer on which a signal line is formed in the X-direction.
FIG. 16G
shows the power-source conductive pattern
100
c
arranged on the
2
a
M layer on which a signal line is formed in the X-direction.
Each of
FIGS. 17A and 17C
is a plan view schematically illustrating a conductive pattern formed on each layer.
FIG. 17A
shows the power-source pattern
100
a
arranged on the layer on which a signal line is formed in the Y-direction.
FIG. 17B
shows the power-source pattern
100
b
arranged on the layer connected to the ground.
FIG. 17C
shows the power-source pattern
100
c
arranged on the layer on which the signal line formed in the Y-direction. Three power-source via holes
112
a
are arranged in the power-source conductive pattern
100
a
, as shown in FIG.
17
A. Three power-source via holes
112
b
are arranged in the power-source conductive pattern
100
b
, as shown in FIG.
17
B. Three power-source via holes
112
c
are arranged in the power-source conductive pattern
100
c
, as shown in FIG.
17
C. That is, the power-source via holes
112
a
to
112
c
are positioned in such a way that the projected positions of the power-source via holes
112
a
to
112
c
are not aligned with each other when the power-source conductive patterns
100
a
to
100
c
are piled up.
The power-source conductive patterns
100
a
to
100
c
are piled up in the order shown in
FIGS. 16A
to
16
I. The power-source via holes
112
a
to
112
c
respectively formed in the power-source conductive patterns
100
a
to
100
c
are of the same type of conductive pattern. For example, the power-source via hole
112
a
in the power-source conductive pattern
100
a
disposed on a layer having signal lines formed in the Y-direction is electrically connected to only the power-source via hole
112
a
in the power-source conductive pattern
100
a
disposed on another layer. In other type of conductive pattern, that is, both the power-source via hole
112
b
formed on the power-source conductive pattern
100
b
and the power-source via hole
112
c
formed on the power-source conductive pattern
100
c
are not electrically connected to the power-source via hole
112
a
in the power-source conductive pattern
100
a
because the power-source via hole
112
a

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