Semiconductor integrated circuit

Details Semiconductor integrated circuit Semiconductor integrated circuit

1999-05-18

2002-06-11

Potter, Roy (Department: 2822)

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Of specified material other than unalloyed aluminum

C257S775000, C257S776000

Reexamination Certificate

active

06404056

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor integrated circuit. More specifically, the present invention relates to a semiconductor integrated circuit including a plurality of semiconductor element groups each having prescribed function, and first, second and third interconnection patterns stacked successively on the plurality of semiconductor element groups.
2. Description of the Background Art
In a semiconductor memory of mega bit order, especially in dynamic random access memories (hereinafter referred to as DRAMs), memory array architecture employing two layers of aluminum interconnection patterns Al
1
and Al
2
is dominant, as described in ESSCIRC PROCEEDINGS, September 1991 pp. 21-24.
FIG. 25
is a block diagram showing a structure of a conventional DRAM chip. Referring to the figure, the DRAM chip includes a plurality of memory array regions
31
and peripheral circuit region
32
provided between the memory array regions. Each memory array region
31
includes a plurality of sub arrays
33
arranged in the row direction, a plurality of sense amplifier bands
34
provided between and at opposite ends of sub arrays
33
, a row decoder
35
and a column decoder
36
. Peripheral circuit region
32
includes a plurality of NAND gates, NOR gates and the like.
The DRAM chip is, specifically, formed of a silicon substrate, a plurality of transistors and capacitors formed on the surface of the silicon substrate, and an interconnection pattern W of metal having high melting point and aluminum interconnection patterns Al
1
and Al
2
stacked successively thereon.
FIG. 26
shows an example of a specific structure of the memory array region
31
of the DRAM chip shown in
FIG. 25
, which is a partial plan view showing the configuration of the sub array
33
and sense amplifier band
34
. Referring to the figure, sub array
33
employs folded bit line structure and includes a plurality of memory cells MC arranged in the directions of rows and columns, and sense amplifier band
34
includes a plurality of sense amplifiers
34
a
provided corresponding to respective columns. In this region, the first layer of the high melting point metal interconnection pattern W is used as bit lines BL and /BL for connecting memory cells MC of each column to a sense amplifier
34
a
. The second layer, that is, the aluminum interconnection pattern Al
1
is used as a part of a word line WL, and serves as a shunt for reducing time constant of the word line WL. The third layer, that is, the aluminum interconnection pattern Al
2
is used as a column selection line CSL for transmitting an output from column decoder
36
.
Bit lines BL and /BL are formed of the interconnection pattern W of metal having high melting point, in order to prevent migration of the material of bit lines BL and /BL to the silicon substrate. As the metal having high melting point, tungsten silicide (WSi) is used, as an example.
Though bit lines BL and /BL must have low resistance so as to increase the speed of data reading, what is more desirable is to reduce capacitance of the bit lines BL and /BL themselves to reduce power consumption, to increase the amount of read signal from memory cell MC so as to ensure operation margin, and to reduce capacitance between bit lines BL and /BL to reduce noise between bit lines BL and /BL, and therefore bit lines BL and /BL, that is, the interconnection pattern W of metal having high melting point, is made thin.
FIG. 27
shows an example of a specific structure of peripheral circuit region
32
of the DRAM chip shown in
FIG. 25
, and it is a partial plan view showing the layout of an area including a 2-input CMOS-NAND gate (hereinafter simply referred to as an NAND gate).
FIG. 28
is an enlarged view of a main portion of FIG.
27
. Referring to the figure, the NAND gate includes P channel MOS transistors P
1
and P
2
and N channel MOS transistors N
1
and N
2
arranged in two rows and two columns, and each of the transistors P
1
, P
2
, N
1
and N
2
includes a gate G extending in the Y direction in the figure and a source S and a drain D provided at opposing sides thereof. At one end of the gate G of each of the transistors P
1
, P
2
, N
1
and N
2
, there is provided a pad PD, and pads PD of P channel MOS transistors P
1
and P
2
and pads PD of Nchannel MOS transistors N
1
and N
2
are provided adjacent to each other.
The third layer, that is, aluminum interconnection pattern Al
2
used as the column selection line CSL in memory array region
31
is used in peripheral circuit region
32
, as power supply lines VL and VL′ and signal lines SL
1
, SL
2
, . . . ; SL
1
′, SL
2
′, . . . , extending in the X direction in the figure. Power supply line VL is provided to cover a P region in which two P channel MOS transistors P
1
and P
2
are arranged, and to the power supply line VL, power supply potential Vcc (H level) is applied. Power supply line VL′ is provided to cover an N region in which two N channel MOS transistors N
1
and N
2
. are arranged, and to the power supply line VL′, power supply potential Vss (L level) is applied.
Signal lines SL
1
, SL
2
, . . . are provided outward from power supply line VL with a prescribed pitch therebetween, and these lines are used for signal input/output between the NAND gate portion and the outside. Signal lines SL
1
′, SL
2
′, . . . are provided outward from power supply line VL′ with a prescribed pitch, and they are used for signal input/output between the NAND gate and the outside.
The second layer, that is, the aluminum interconnection pattern Al
1
used as the shunt of word line WL in memory array region
31
is used, in this region, as a local line LL for internal connection of NAND gate.
More specifically, P channel MOS transistors P
1
and P
2
have their sources connected to local lines LL
2
and LL
3
, respectively, through contact holes CH, while local lines LL
2
and LL
3
are connected via through holes TH to power supply line VL. P channel MOS transistors P
1
and P
2
and N channel MOS transistor N
1
have their drains D connected to local line LL
4
through contact holes CH, and local line LL
4
is connected to signal line SL
1
′, for example, via a through hole TH. Signal line SL
1
′ serves as an output signal line for the NAND gate.
The source S of N channel MOS transistor N
1
and the drain D of N channel MOS transistor N
2
are commonly connected to local line LL
5
through contact holes CH. N channel MOS transistor N
2
has its source connected to local line LL
6
through a contact hole CH, and local line LL
6
is connected to power supply line VL′ via a through hole TH.
P channel MOS transistor P
1
and N channel MOS transistor N
1
have their gates G commonly connected to local line LL
1
through pads PD and contact holes CH, and local line LL
1
is connected to signal line SL
2
, for example, via through hole TH. Signal line SL
2
serves as one input signal line A of the NAND gate.
P channel MOS transistor P
2
and N channel MOS transistor N
2
have their gates G commonly connected to local line LL
7
through pads PD and contact holes CH, and local line LL
7
is connected to signal line CL
3
′, for example, via through hole TH. Signal line SL
3
′ serves as the other input signal line B of the NAND gate.
Transistors P
1
, P
2
, N
1
and N
2
constitute an electric circuit such as shown in
FIG. 29
, that is, a NAND gate generally represented by such signs as shown in FIG.
30
.
In the conventional DRAM chip, the first layer, that is, the interconnection pattern W of metal having high melting point is used as bit lines BL and /BL in the memory array region
31
, while it is hardly utilized in the peripheral circuit region
32
. The reason for this is that the conventional interconnection pattern W of metal having high melting point which is formed of tungsten silicide (WSi) has high sheet resistance, resulting in significant signal delay when it is used as the local line LL for connecting transi

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