Static information storage and retrieval – Floating gate – Particular connection
Reexamination Certificate
2000-10-31
2002-12-24
Zarabian, A. (Department: 2824)
Static information storage and retrieval
Floating gate
Particular connection
C365S201000
Reexamination Certificate
active
06498749
ABSTRACT:
BACKGROUND OF THE INVENTION
Non-volatile memories, like flash EEPROMs, are capable of retaining information indefinitely, also when the memory receives no power. Although information is retained indefinitely, some loss of information may still occur due to memory errors. Such errors will be small in number. Therefore it is possible to detect and correct these errors with a limited amount of redundant information for a large number of data units in the non-volatile memory. However, because redundant information is used for a large number of data units, detection and correction require reading a large number of data units from the memory.
U.S. Pat. No. 5,719,808 (Harari et al.) teaches a flash EEPROM circuit that corrects such errors. The flash EEPROM of Harari et al. operates in the manner of a disk drive, reading a file of data at a time. The memory contains EEPROM memory locations for the data of the file, EEPROM memory locations for a header of the file, a defect map and error correcting code data. Furthermore, spare memory locations are provided for corrected data for data units that have been found to be in error in the memory. The circuit uses DMA to transfers a series of data units from a file. At the start of DMA the circuit first loads the defect map into a defect pointer memory file. Subsequently the circuit reads successive data units from the file. If the defect map indicates that a data unit contains an error, the corrected data from a spare location is substituted for the data unit. Once a block of data has been read from the memory, the data from the block and the error correcting code data is used to locate and correct errors in the block. Information indicating the memory location that contains an error is stored in the defect map and the corrected information is stored in a spare memory location. When the memory location is accessed again in a subsequent DMA operation, the circuit notes from the defect map in the defect pointer memory file that the memory location is in error. In response thereto the circuit uses the corrected information from the spare memory location.
Harari et al. note that a flash EEPROM develops an increasing number of defects during its life cycle. Eventually these errors might overwhelm the error correcting capacity of the error correcting code. To prevent this from happening, Harari et al. correct errors each time the file is read and store corrected information when the errors are identified during reading a data block. Thus, the number of uncorrected errors will not usually becomes so large as to exceed the error correcting capacity of the error correcting code.
Harari et al. do not consider reading of data units outside the context of a file. Data units can only be read as part of a file. If a single data unit is needed, the error correcting code can be used only if a large amount of unnecessary information from the file is read together with the data unit.
SUMMARY OF THE INVENTION
Amongst others, it is an object of the invention to provide for correction of errors in a non-volatile memory were data units are randomly accessed during use, not as part of reading a whole file.
According to the invention, the circuit detects and corrects errors in the non-volatile memory autonomously from access to the memory by the processor for normal use the data. In addition, error correction may be triggered by read errors that occur when the processor accesses the memory to read data. Preferably the correction is triggered start-up of the circuit, or periodically during use, triggered like refresh cycles in a DRAM. Thus, error correction is performed during memory use and its activation does not depend on normal access to data units.
REFERENCES:
patent: 5532962 (1996-07-01), Auclair et al.
patent: 5719808 (1998-02-01), Harari et al.
patent: 6131177 (2000-10-01), Takeuchi
patent: 0392895 (1990-10-01), None
patent: 0926687 (1999-06-01), None
patent: 9620443 (1996-07-01), None
“VLSI Implementation of a Self-Checking Self-Exercising Memory System”, by David A. Rennels et al., pp. 170-177.
Cuppens Roger
Vlot Marnix Claudius
Koninklijke Philips Electronics , N.V.
Waxler Aaron
Zarabian A.
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