Multi-tier point-to-point buffered memory interface

Details Multi-tier point-to-point buffered memory interface Multi-tier point-to-point buffered memory interface

2000-12-28

2002-12-10

Hoang, Huan (Department: 2818)

Static information storage and retrieval

Interconnection arrangements

C365S051000, C365S052000, C365S230030

Reexamination Certificate

active

06493250

ABSTRACT:

FIELD OF THE INVENTION
This present invention relates generally to digital memory devices and systems, and more particularly to bus architectures and bus communication methods for such devices and systems.
BACKGROUND OF THE INVENTION
Microprocessors, digital signal processors, digital imaging devices, and many other types of digital data processing devices rely on an attached high-speed memory system to hold data and/or processor instructions needed by the processing device. As these processing devices become faster and more powerful, the increased demands placed on them generally translates to a need for larger and faster attached memory systems.
FIG. 1
depicts a typical memory system configuration. One or more memory devices
26
AA,
26
AB,
26
BA,
26
BB,
26
CA,
26
CB interface with a memory controller
20
through a memory bus
22
. A host (e.g., a central processing unit (CPU), not shown) also connects to memory controller
20
through a front-side bus FSB. The memory devices hold data in arrays of addressable memory cells. Memory controller
20
controls the exchange of data between the host and the memory storage devices.
Memory bus
22
carries memory signals on a set of signal lines. Memory signals fall generally into one of several categories including clock and control signals, address signals, command signals, and data signals. Data signals carry the actual data that will be stored in, or retrieved from, a memory device. Address signals specify the location within a memory device where data is to be read from or written to, and may also select which of several memory devices is to be accessed. Command signals instruct a memory device as to what type of operation is to be performed, e.g., read, write, refresh, and possibly as to which of several access modes (such as a burst mode) should be used for a data transfer. Clock and control signals synchronize the other signals passing between controller
20
and the memory devices. Although memory bus
22
may use a separate signal line for each memory signal (e.g., 32 address lines to transfer a 32-bit-wide address in one clock cycle and 32 data lines to transfer a 32-bit-wide data word in one clock cycle), various schemes also exist to re-use one or more signal lines for different memory signals during different clock cycles of a memory transaction.
In the configuration shown in
FIG. 1
, memory bus
22
is a multi-drop memory bus. In other words, bus
22
is arranged with a backbone of signal lines. A signal line stub, or “drop”, connects each of the memory devices to the backbone. Typically, memory bus
22
will comprise a collection of leads routed on a printed circuit board
21
known as the “main board” or “motherboard”. Memory controller
20
mounts to motherboard
21
and connects to one end of the leads comprising memory bus
22
. Each drop of memory bus
22
connects to an electrical terminator, or socket. A typical main board contains multiple memory sockets, e.g., the three sockets
28
A,
28
B, and
28
C shown in FIG.
1
.
Memory is added to the memory system by inserting memory modules (e.g.,
24
A,
24
B,
24
C) into one or more of the sockets. One popular type of memory module is a Dual In-line Memory Module, or DIMM. The DIMM is a rectangular low-profile circuit board that has electrical contact points arranged on both sides along one long edge. The contact points form electrical connections to the main board's memory bus when the DIMM is inserted into a DIMM memory socket.
A DIMM generally has multiple individual memory devices mounted to it. The devices all work in parallel to perform memory functions. For instance, a DIMM may have eight memory devices, each of which receives the same memory address from the controller. If the size of a data word is 32 bits, each of the memory devices is responsible for four bits of the data word that is placed on the memory bus. The DIMMs depicted in
FIG. 1
are dual-bank DIMMs, i.e., an “A” bank and a “B” bank of memory devices reside on the DIMM. The A bank and the B bank occupy logically separate areas of memory space, such that each bank can be addressed separately.


REFERENCES:
patent: 5959923 (1999-09-01), Matteson et al.
patent: 6223301 (2001-04-01), Santeler et al.
patent: 6256221 (2001-07-01), Holland et al.
patent: 6147921 (2001-11-01), Novak et al.

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