Translation lookaside buffer control system

Details Translation lookaside buffer control system Translation lookaside buffer control system

1987-12-23

1990-10-02

Fleming, Michael R.

Boots, shoes, and leggings

3642434, 3642543, 3642563, G06F 1208

Patent

active

049611356

ABSTRACT:
A virtual address register for storing a virtual address is arranged in a translation lookaside buffer control system. An artihmetic operation circuit is coupled to the virtual address register and performs adding, EX-ORing, and the like of the contents of two first fields which do not overlap each other. A TLB address register is coupled to the arithmetic operation circuit and the virtual address register, and stores the contents of a second field which does not overlap those of the first fields and output data from the arithmetic operation circuit. A translation lookaside buffer (TLB) is coupled to the TLB address register. The TLB is addressed by the content of the address register, stores address translation data in each entry, and translates a virtual address into a physical address, at high speed. A controller is coupled to the virtual address register and the TLB address register, and determines whether a virtual address specified by the address translation data stored in the entry designated by the contents of the TLB address register coincides with the virtual address stored in the virtual address register. The controller replaces the contents of a corresponding entry of the TLB when the virtual addresses do not coincide with each other.

REFERENCES:
patent: 4373179 (1983-02-01), Katsumata
patent: 4521846 (1985-06-01), Scalzi et al.
patent: 4654777 (1987-03-01), Nakamura
patent: 4731740 (1988-03-01), Eguchi
patent: 4802084 (1989-01-01), Ikegaya et al.

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