Single-chip microcontroller with efficient peripheral testabilit

Details Single-chip microcontroller with efficient peripheral testabilit Single-chip microcontroller with efficient peripheral testabilit

1993-08-31

1995-06-27

Harvey, Jack B.

Excavating

371 161, 371 225, G06F 1130

Patent

active

054287707

ABSTRACT:
A single-chip microcontroller (30) includes a central processing unit (CPU) (31) and several memory-mapped peripherals (32, 33, 34, 35) connected to internal address (37) and data (38) buses. The microcontroller (30) includes a test port (40) for receiving test data and providing the test data to the address (37) and data (38) buses to access the memory-mapped peripherals (32, 33, 34, 35) directly. The microcontroller (30) thus allows testing of the memory-mapped peripherals (32, 33, 34, 35) without CPU overhead, significantly reducing test time. The test port (40) includes a shift register (44) which selectively updates address high, address low, and data fields using the test data so that a field need not be re-entered if it doesn't change between test cycles. The test port (40) receives the test data and test control signals via signal lines shared with a general purpose input/output (GPIO) port (33) and requires only one independent control signal line.

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