Semiconductor device manufacturing: process – Chemical etching – Vapor phase etching
Reexamination Certificate
2000-07-12
2002-11-26
Goudreau, George (Department: 1763)
Semiconductor device manufacturing: process
Chemical etching
Vapor phase etching
C430S005000, C438S704000, C438S705000, C438S734000, C438S746000, C438S750000
Reexamination Certificate
active
06486074
ABSTRACT:
TECHNICAL FIELD
This invention relates to methods of masking and etching semiconductor substrates, and to ion implant lithography methods of processing semiconductor substrates.
BACKGROUND OF THE INVENTION
Integrated circuitry fabrication typically involves lithographic processing to transfer patterns formed in an imaging layer to underlying substrate material which will form part of the finished circuitry. For example, an imaging layer such as conventional photoresist material is provided over a layer to be patterned by etching. The photoresist layer is then masked or otherwise processed such that selected regions of the imaging layer extending entirely therethrough are exposed to suitable conditions which impact the solvent solubility of the exposed regions versus the unexposed regions. For example, the selected regions of the photoresist can be exposed to actinic energy, ion implantation, or yet-to-be-developed processes. The imaging layer is then typically solvent processed to remove one or the other of the processed or the non-processed regions, thereby forming the imaging layer to have mask openings extending entirely therethrough to the underlying layer to be patterned. The substrate is then typically subjected to a suitable etching chemistry which is selected to etch the underlying layer or layers and not the imaging layer, thereby transferring the imaging pattern to the underlying circuitry layer or layers.
One type of masking or imaging layer processing comprising ion beam lithography. Here, suitable ions such H
+
or He
+
are implanted into selected regions of a photoresist or other imaging layer. The implant species and energy are selected such that the implanting occurs entirely through the imaging layer and slightly into the underlying layer to be etched to ensure the complete transformation of the implanted regions entirely through the imaging layer. Subsequent wet solvent processing is conducted which completely removes selected portions of the imaging layer forming openings entirely therethrough to the underlying layer to be etched.
Integrated circuitry fabrication continues to strive to produce denser and denser circuitry and thereby smaller and smaller individual components. This has typically been accompanied by an increase of the heights of the masking features in the imaging layer as compared their widths, something referred to as “aspect ratio”. Unfortunately, this can result in a comparatively small degree of surface area for adhesion of the masking layer to the underlying layer as compared to its height at the conclusion of patterning. This can lead to toppling or displacement of the individual masking blocks by the solvent processing and cleaning processes. If the individual masking blocks become displaced or topple onto one another, the underlying layer is not properly etched to produce the desired circuitry, typically leading to fatal flaws therein.
It would be desirable to overcome this adverse processing phenomenon.
SUMMARY
The invention includes methods of masking and etching semiconductor substrates, and to ion implant lithography methods of processing semiconductor substrates. In one implementation, a method of masking and etching a semiconductor substrate includes forming a layer to be etched over a semiconductor substrate. An imaging layer is formed over the layer to be etched. Selected regions of the imaging layer are removed to leave a pattern of openings extending only partially into the imaging layer. After the removing, the layer to be etched is etched using the imaging layer as an etch mask.
In one implementation, an ion implant lithography method of processing a semiconductor includes forming a layer to be etched over a semiconductor substrate. An imaging layer of a selected thickness is formed over the layer to be etched. Selected regions of the imaging layer are ion implanted to change solvent solubility of implanted regions versus non-implanted regions of the imaging layer, with the selected regions not extending entirely through the imaging layer thickness. The ion implanted regions of the imaging layer are removed to leave a pattern of openings extending only partially into the imaging layer. After the removing, the layer to be etched is etched using the imaging layer as an etch mask.
REFERENCES:
patent: 4377437 (1983-03-01), Taylor et al.
patent: 5853925 (1998-12-01), Huh
patent: 6042996 (2000-03-01), Lin et al.
patent: 61-177720 (1961-08-01), None
patent: 59-053842 (1984-03-01), None
“The Range of Light Ions In Polymeric Resist”, Adesida et. al. (1984); J. Appl. Phys. 56(6), pp. 1801-1807.*
“A Review of Ion Projection Lithography”, Melngailis et. al.; J. Vac. Sci. Tech. B (1998); 16(3); pp. 927-957.*
U.S. patent application Ser. No. 09/444280, Reinberg, pending.
Goudreau George
Micro)n Technology, Inc.
Wells St. John P.S.
LandOfFree
Methods of masking and etching a semiconductor substrate,... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Methods of masking and etching a semiconductor substrate,..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Methods of masking and etching a semiconductor substrate,... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2950702