Method and apparatus for pattern recognition of wafer test bins

Details Method and apparatus for pattern recognition of wafer test bins Method and apparatus for pattern recognition of wafer test bins

1997-06-27

1998-07-28

Mancuso, Joseph

Image analysis

Applications

Manufacturing or product inspection

438 10, 438 17, H01L 2166

Patent

active

057871906

ABSTRACT:
An automated system and procedure processes wafer test bin data of semiconductor wafers to formulate a fault pattern at statistically significant levels. A processor such as a neural engine or neural network collects wafer test bin results to generate a N/N wafer map to be correlated with wafer maps produced from a wafer electrical test, a wafer level reliability test, and an in-line defect analysis. A N/N wafer map generated by the processor is cross-checked with a wafer map generated from another semiconductor tester to formulate possible overlap fault patterns. The confirmed fault patterns are further analyzed by performing failure analysis to find the root cause of fault patterns. A report containing fault patterns and the root cause for fault patterns is sent back to a fab for making adjustment to the fabrication process to increase the overall yield of the future batch of semiconductor wafers. The report is also stored in a pattern database to serve as a library for future reference of previously recognized fault patterns, thereby to bypass the need to perform a failure analysis for matching fault patterns.

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Dave Wilson et al., Automatic In-Line to End-of-Line Defect Correlation Using FSRAM Test Structure for Quick Killer Defect Identification, Proc. IEEE, pp. 160-163, Mar. 1994.
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