Scheduling of direct memory access

Details Scheduling of direct memory access Scheduling of direct memory access

1998-04-01

2002-10-29

Courtenay, III, St. John (Department: 2151)

Electrical computers and digital processing systems: multicomput

Computer-to-computer data routing

Least weight routing

C710S022000

Reexamination Certificate

active

06473780

ABSTRACT:

This invention relates to microprocessor systems, and more specifically, to an improved technique of scheduling direct memory access (“DMA”) in microprocessor systems.
BACKGROUND OF THE INVENTION
Direct memory access (“DMA”) is a technique utilized in microprocessor systems and often employed in real time embedded digital signal processing systems. DMA involves the transfer of information from one portion of memory to another in an efficient manner without reading such information through the Central Processing Unit (CPU) of the main microprocessor system. The use of DMA channels facilitates fast transfer of large amounts of information between portions of system memory without occupying large amounts of CPU overhead. Typically, DMA transfer occurs at a predetermined static priority level with respect to the execution of application software programs within the DSP. The application programs, also called “core jobs”, are typically given higher priority than the DMA jobs with respect to memory access.
Such prior art systems are sub-optimal because they fail to account for the fact that some DMA jobs may have higher priority than some core jobs. Additionally, the DMA jobs themselves may have different priorities with respect to each other and the priorities may be different from the chronological order in which the DMA jobs arrive. None of this is taken into account in present systems, and thus, there results an inability to use DMA channels to transfer data in hard real time systems without a degradation in system performance and reliability.
SUMMARY OF THE INVENTION
The above and other problems of the prior art are overcome in accordance with the present invention which relates to a technique of both individually prioritizing DMA jobs, as well as prioritizing DMA jobs with respect to core jobs. In this manner, DMA jobs may preempt lower priority DMA jobs and DMA jobs and core jobs may preempt each other. Such a system results in the highest priority task, be it core or DMA, being given access to memory at any given time.
In an enhanced embodiment, DMA priorities may be adjusted slightly higher or lower than a specific core job. Such core job could be, for example, the core job which spawned the DMA task. Such adjustment allows for the DMA job to run in the background while the core job which spawned the DMA job runs in the foreground or vice versa. Additionally, core jobs could be prioritized as 1, 3, 5, 7, etc., while DMA jobs are prioritized as 2, 4, 6, and 8. This provides a system where core jobs and DMA jobs may run in a foreground/background mode, either the core or the DMA job running in the foreground, and the other running in the background.
In another enhanced embodiment, a scheduler/arbitrator sequentially polls DMA job queues and core job queues, and executes jobs from each in accordance with a priority number assigned to the job. Each queue has its highest priority tasks at the top thereof, so that only a task with equal or higher priority from the other queue can preempt execution of such highest priority task.


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