Miscellaneous active electrical nonlinear devices – circuits – and – Specific identifiable device – circuit – or system – With specific source of supply or bias voltage
Reexamination Certificate
2001-01-12
2002-08-06
Zweizig, Jeffrey (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Specific identifiable device, circuit, or system
With specific source of supply or bias voltage
C327S308000
Reexamination Certificate
active
06429729
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor integrated circuit device, and in particular to a configuration generating an optimal voltage in accordance with variation of process conditions.
2. Description of the Background Art
In order to reduce the power consumption of a semiconductor integrated circuit device, it is effective to lower an operating power-supply voltage. This is because, when the operating power-supply voltage is lowered, charging/discharging current of a load capacitance is reduced by the amount of the reduction of the voltage. Thus, as the power-supply voltage is lowered, the power consumption is reduced in proportional to the square of the reduction rate of the voltage.
For example, in a widely-used general-purpose memory, the gate length of a transistor is scaled down to near the limit of micro-fabrication, and an internal power potential of a memory is down-converted by an on-chip voltage down converter while a general-purpose LSI (Large Scale Integration) and an external power-supply voltage are kept equal to each other. This can realize high reliability and low power consumption. Further, by the voltage down converter, a constant internal power potential can also be obtained, and hence a stable operation can be realized without being affected by variation of the external power-supply voltage.
A conventional voltage down converter is now described with reference to FIG.
16
. Sub-voltage down converter shown in
FIG. 16
includes a constant-current generating circuit
3
, a reference voltage generating circuit
4
A and a current mirror amplifier
5
.
Constant-current generating circuit
3
generates a signal ICONST and a signal BIAS. Constant-current generating circuit
3
generates a stable internal voltage compared to an external voltage, and yet has a circuit configuration capable for keeping a temperature variation of the system to be minimum. Constant-current generating circuit
3
includes transistors TrP-
1
, TrP-
2
, TrN-
1
and TrN-
2
, and a resistor Rt. Transistors TrP-
1
and TrP-
2
are PMOS transistors, whereas transistors TrN-
1
and TrN-
2
are NMOS transistors.
Transistor TrP-
1
is connected between a power-supply voltage and a node ICONST. Resistor Rt and transistor TrP-
2
are connected in series between the power supply voltage and node BIAS. The respective gates of transistors TrP-
1
and TrP-
2
are connected to node ICONST. Transistor TrN-
1
is connected between node ICONST and a ground voltage, and transistor TrN-
2
are connected between node BIAS and a ground voltage. The respective gates of transistors TrN-
1
and TrN-
2
are connected to node BIAS. A signal ICONST is output from node ICONST, and a signal BIAS is output from node BIAS.
Transistors TrN-
1
and TrN-
2
are formed as transistors having the same size and either of the gates is connected to node BIAS, such that the same current I flows on the transistors TrP-
1
and TrN-
1
side, and the transistors TrP-
2
and TrN-
2
side.
Transistors TrP-
1
and TrP-
2
are formed to have the gate lengths L equal to each other and the gate widths W with a ratio of 1:10. A voltage difference &Dgr;V which is made upon a voltage drop, generated when the same current flows in both transistors, is converted into current I (=&Dgr;V/Rt). Because resistance Rt requires a large value on the order of several hundred k&OHgr;, an interconnection resistance obtained by adjusting the length of gate interconnection materials of the transistor may be used.
Transistors TrP-
1
and TrP-
3
are formed to have the same size, so that current I is transmitted to the reference voltage generating circuit. At the same time, feed back is provided for the current flowing at transistors TrP-
1
and TrP-
1
side and at transistors TrP-
2
and TrN-
2
side. This feed back effect enables the system to transfer an optimal constant current I to the reference voltage generating circuit while monitoring the state of output all the time.
Reference voltage generating circuit
4
A includes transistors TrC-
1
to TrC-
5
, TrP-
3
, and TrP-
4
. Transistor TrP-
3
is connected between a power-supply voltage and a node Vref outputting a reference voltage Vref, and receives signal ICONST at the gate thereof Transistors TrC-
5
, TrC-
1
, TrC-
2
, TrC-
3
and TrC-
4
are connected in series between node Vref and a node Z
0
, the respective gates thereof being grounded. Transistor TrP-
4
is connected between node Z
0
and a ground potential, the gate thereof being grounded.
Switches SW
1
to SW
4
are respectively arranged for transistors TrC-
1
to TrC-
4
. When a switch SWi (i=1 to 4) is turned on, the drain and the source of a transistor TrC-i are connected.
A channel resistance including transistors TrC-
1
to TrC-
4
and TrC-
5
are denoted by Rc. (I×Rc+Vtp) is output as a reference voltage Vref, which is a sum of a potential difference I×Rc at channel resistance Rc receiving current I and a potential difference Vtp, substantially corresponding to a threshold voltage of transistor Trp-
4
, at transistor TrP-
4
generated when current I flows. The threshold of transistor TrP-
4
is hereinafter referred to as Vtp.
Current mirror amplifier
5
includes a main amplifier
1
having a large driving power operated when an internal circuit driven by an output Int.Vcc is activated, and a sub-amplifier
2
having a small driving power which is constantly operated.
Main amplifier
1
includes PMOS transistors TrP-
10
, TrP-
11
, Ti and T
5
, and NMOS transistors TrN-
3
, TrN-
10
and TrN-
11
. Sub-amplifier
2
includes PMOS transistors TrP-
10
, TrP-
11
and T
2
, and NMOS transistors TrN-
3
, TrN-
10
and TrN-
11
.
Main amplifier
1
is now described. Transistor TrP-
10
is connected between a power-supply voltage and a node COMPA, and transistor TrP-
11
is connected between a power-supply voltage and a node Z
11
, and the respective gates of transistors TrP-
10
and TrP-
11
are connected to a node Z
11
.
Transistor TrN-
10
is connected between node COMPA and a node Z
12
, and receives reference voltage Vref at the gate thereof. Transistor TrN-
11
is connected between node Z
11
and node Z
12
, and the gate thereof is connected to a node OUT outputting an internal power-supply voltage int.Vcc. Transistor TrN-
3
is connected between node Z
12
and a ground voltage, and receives an activation signal ACT for making the gate to operate the internal circuit.
Transistor T
1
is connected between the power-supply voltage and node COMPA, and receives activation signal ACT at the gate thereof. Transistor T
5
is connected between the power-supply voltage and node OUT, and the gate thereof is connected to node COMPA.
Sub-amplifier
2
is now described. A connecting node of transistors TrP-
10
and TrP-
11
is referred to as a node COMPS. Transistors TrP-
10
, TrP-
11
, TrN-
10
, TrN-
11
and TrN-
3
are connected as described above. Transistor TrN-
3
in sub-amplifier
2
receives signal BIAS output from constant-current generating circuit
3
. Transistor T
2
is connected between the power-supply voltage and node OUT, and the gate thereof is connected to node COMPS.
An amplifier is an important circuit determining the driving power of the system, and a constant-current generating circuit and a reference voltage generating circuit are greatly important for minimizing variation of an internal potential for a change of a temperature or an external voltage, and are very delicate for changes of various conditions. The properties of the constant-current generating circuit and the reference voltage generating circuit determine the operational property of the system.
In reference voltage generating circuit
4
A, channel resistance Rc is formed from a transistor having a long gate length. To generate a desired reference voltage Vref independent of variation in a resistance value for a threshold due to process variation, combinations of on/off of switches SW
1
to SW
4
can change the value of channel resistance Rc in 16 stages.
If the ratio of the g
Akiyama Mihoko
Fujii Nobuyuki
Kobayashi Mako
Morishita Fukashi
Taito Yasuhiko
McDermott & Will & Emery
Mitsubishi Denki & Kabushiki Kaisha
Zweizig Jeffrey
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