Semiconductor device

Details Semiconductor device Semiconductor device

2001-03-09

2002-10-15

Nguyen, Viet Q. (Department: 2818)

Static information storage and retrieval

Floating gate

Particular biasing

C365S185260, C365S185140, C365S185050, C365S185010

Reexamination Certificate

active

06466482

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor integrated circuit (semiconductor device) including electrically erasable and programmable non-volatile memory elements and, more particularly, to a technology effectively applied to, for example, a microcomputer or a memory LSI in which non-volatile memory elements, which are capable of being mounted without adding a new process to an existing CMOS process and formed by applying a single layer poly flash technology, are applied to a fault recovery and the like.
A single layer poly flash technology constituting the memory cell of a non-volatile memory by a single layer poly silicon gate is disclosed in Japanese Patent Laid-Open No. 334190/1994 (which corresponds to U.S. Pat. No. 5,465,231), U.S. Pat. Nos. 5,440,159, 5,504,706, Japanese Patent Laid-Open No. 212471/1992 (which corresponds to U.S. Pat. Nos. 5,457,335, 5,767,544 and 6,064,606), and “A Single Poly EEPROM Cell Structure for Use in Standard CMOS Processes”, IEEE Journal of Solid State Circuits, VOL. 29, NO. 3, March 1994, pp. 311-316. For example, in a non-volatile memory cell by a single layer poly flash technology disclosed in Japanese Patent Laid-Open No. 334190/1994, a first conductivity type MOS transistor is formed on a semiconductor substrate and a plate electrode is formed in a second conductivity type well via an insulating layer, wherein the gate electrode of the MOS transistor and plate electrode are connected to each other and function as a floating gate and wherein the second conductivity type well functions as a control gate.
In Japanese Patent Laid-Open No. 212471/1992, there is also disclosed a technology for utilizing an electrically programmable non-volatile memory (EPROM) as a recovery circuit of a read on memory (ROM). Further, it is described in the patent gazette that a non-volatile memory element having a first layer gate structure in accordance with the present invention can be also used as an electrically programmable and erasable non-volatile memory element, in which a write operation is performed by hot carriers and an erase operation is performed by a tunnel current produced by applying a high voltage to a source or a drain, or the write and erase operations are performed by the tunnel current.
On the other hand, a technology for differentially utilizing two non-volatile memory elements from the viewpoint of preventing a malfunction is disclosed in Japanese Patent Laid-Open No. 163797/1992, Japanese Patent Laid-Open No. 263999/1989, Japanese Patent Laid-Open No. 74392/1992, Japanese Patent Laid-Open No. 127478/1990, Japanese Patent Laid-Open No. 129091/1992, Japanese Patent Laid-Open No. 268180/1994, and U.S. Pat. No. 5,029,131. In a differential type memory cell structure, one non-volatile memory element is set in a writing state and the other non-volatile memory element is set in an erasing state and signals read out in parallel from both the non-volatile memory elements are differentially amplified and the logic value of memory information is judged according to which output of the non-volatile memory elements in the writing state or in the erasing state becomes either an input to an inversion side or a non-inversion side.
SUMMARY OF THE INVENTION
The present inventor has studied a differential type non-volatile memory cell structure and found the following points. That is, the present inventor has found that, even in the differential type non-volatile memory cell structure, there is presented a problem that the rate of occurrence of faulty reading caused by degradation in a charge holding characteristic is largely affected by a threshold voltage at the initial state where a floating gate has no charge, a threshold voltage in a writing state or in an erasing state, and the state of a word line electric potential when a read operation is performed. Here, FIG.
49
and
FIG. 50
which will be hereinafter described are not the drawings showing publicly known technologies, but the drawings made by the present inventor for the purpose of facilitating the understanding of the present invention.
In
FIG. 49
, there is illustrated the threshold voltage distribution of a memory cell in the case where an initial threshold voltage (Vthi) is set at a relatively high value. For example, the initial threshold voltage (Vthi) is set at a value higher than the mean value of a low threshold voltage (VthL) in an erasing state and a high threshold voltage (VthH) in a writing state. The initial threshold voltage (Vthi) is a threshold voltage in a state of thermal equilibrium. A read word line electric potential (Vread) is set in the middle region between the low threshold voltage (VthL) and the initial threshold voltage (Vthi). In this setting state, the voltage difference between the high threshold voltage (VthH) and the initial threshold voltage (Vthi) is small, that is, the amount of accumulated charges is small and a self-electric field intensity applied to a gate oxide film is also small. As a result, a decrease in the threshold voltage caused by the leak of charges from the floating gate, that is, data retention resists occurring. On the other hand, an electric field in the direction in which electrons are injected into the floating gate is applied to the tunnel oxide film of the memory cell at the low threshold voltage (VthL) by the word line voltage when the read operation is performed to also generate weak hot electrons near a drain to thereby generate a charge gain, which increases the threshold voltage. Since this undesirable increase limit of the threshold voltage reaches the initial threshold voltage (Vthi), when the threshold voltage is higher than the read word electric potential (Vread), the data is inversed and can not be read out. Therefore, the fact that the characteristic shown in
FIG. 49
is comparatively strong for the data retention but is weak for the charge gain has been made clear by the present inventor.
In contrast to this, in
FIG. 50
, there is illustrated the threshold voltage distribution of the memory cell in the case where the initial threshold voltage (Vthi) is set at a relatively low value. For example, the initial threshold voltage (Vthi) is set at a value lower than the mean value of the low threshold voltage (VthL) and the high threshold voltage (VthH). The read word line electric potential (Vread) is set in the middle region between the high threshold voltage (VthH) and the initial threshold voltage (Vthi). In this setting state, the voltage difference between the low threshold voltage (VthL) and the initial threshold voltage (Vthi) is small and hence the charge gain caused by the word line voltage when the read operation is performed resists occurring. On the other hand, since a memory cell having the high threshold voltage (VthH) has the large voltage difference with respect to the initial threshold voltage (Vthi), it has a large amount of accumulated charges and high self-electric field intensity applied to the gate oxide film. As a result, an undesirable decrease in the threshold voltage easily arises from the leak of charges from the floating gate. Since this undesirable decrease limit of the threshold voltage reaches the initial threshold voltage (Vthi) and when the threshold voltage is lower than the read word line electric potential (Vread), the data is inversed and can not be read out. The fact that since the characteristic shown in
FIG. 50
is comparatively strong for the charge gain and the difference between the low threshold voltage (VthL) and the read word line electric potential (Vread) is large, it can produce a comparatively large read current but is weak for the data retention has been found by the present inventor.
In this manner, the high threshold voltage (VthH) of the non-volatile memory element is caused to gradually approach the initial threshold voltage (Vthi) in the state of thermal equilibrium by the leak of charges (data retention) by the self-electric field applied to the gate oxide film, and the low threshold voltage (VthL) is caused to gradually approach the

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