Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Charge transfer device
Reexamination Certificate
1999-08-06
2002-10-15
Wojciechowicz, Edward (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Charge transfer device
C257S222000, C257S229000, C257S236000, C257S392000, C257S402000
Reexamination Certificate
active
06465819
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a solid state imaging apparatus and a manufacturing method for the same. More particularly, the present invention relates to a solid state imaging apparatus with transistors having different film thickness of gate insulating films and a manufacturing method for the same.
2. Description of the Related Art
A solid state imaging apparatus using a charge coupled device (CCD) is known as a typical example of the solid state imaging apparatus.
FIG. 1
shows the well known CCD solid state imaging apparatus of an interline transfer system.
Referring to
FIG. 1
, the imaging apparatus is composed of an imaging section
101
, a horizontal CCD section
102
extending in a horizontal direction and an output section
103
as a charge detecting section. The imaging section
101
is composed of a plurality of photodiodes (photoelectric converting elements)
104
arranged in a 2-dimensional matrix manner to convert a light signal into a signal charge through photoelectric conversion and to store the signal charge.
Further, a vertical CCD section
105
is adjacent to a column of the photodiodes
104
to transfer the signal charge in a vertical direction. A read section
106
is provided between the photodiode
104
and the vertical CCD section
105
to read the signal charge. A remaining section of the imaging section
101
other than the above-described portions is an element separating region
107
.
Such an imaging apparatus operates as follows. That is, a signal charge is stored through photoelectric conversion by the photodiode
104
for a predetermined time and is read out by the vertical CCD section
105
through the read section
106
. After being read out to the vertical CCD section
105
, the signal charge is transferred to the vertical direction for the horizontal CCD section
102
one line by one line. After being transferred to the horizontal CCD section
102
, the signal charge is transferred to the horizontal direction in the horizontal CCD section
102
, and is detected as an output voltage by the output section (charge detecting section)
103
.
The output section
103
is composed of a detection capacitor as a floating diffusion layer capacitor and an output amplifier which is connected with the detection capacitor. From the viewpoint of impedance conversion, a source follower grounding circuit type amplifier of 2 stages or 3 stages and composed of MOS transistors is used as the output amplifier in many cases. The source follower grounding circuit type amplifier is referred to as a source follower type amplifier, hereinafter.
FIG. 2
schematically shows the floating diffusion layer capacitor as a detection capacitor
108
and a 3-stage source follower amplifier
109
connected with the detection capacitor. A signal charge is transferred in the horizontal CCD section
102
(not shown in FIG.
2
), and is stored into the floating diffusion layer capacitor
108
. The potential change at this time is transmitted to the transistors in the subsequent stage through a driver transistor D
101
in
FIG. 1
in the initial stage of the amplifier. Then, the potential change is outputted from an output terminal Vout.
In this case, the driver transistors are the transistors D
101
, D
102
and D
103
in the source follower type amplifier. In the driver transistor, the source side is connected with a higher potential power supply Vdd. The transistors L
101
, L
102
and L
103
in which the drains are grounded are called load transistors. Moreover, sets of transistors D
101
and L
101
, D
102
an L
102
, and D
103
and L
103
are called the first stage of the amplifier, the second stage, and the third stage, respectively, from the input side to which the floating diffusion layer capacitor
108
is connected. In each set, the drain of the driver transistor and the source of the load transistor are connected with each other.
FIGS. 3A and 3B
show cross sectional structure of the transistor of the output amplifier.
FIGS. 3A and 3B
show the cross sectional structures of the transistors of the first stage of the amplifier and the second or third stage of the amplifier, respectively. A P-type well
111
is formed on an N-type substrate
110
, and the transistor has a source region
112
and drain region
113
which are formed in P-type well
111
as high concentration N-type impurity regions. A gate electrode
115
is formed on the channel between the source region
112
and the drain region
113
through a gate insulating film
114
having the film thickness from about 70 nm to about 85 nm. Thus, the transistor is formed.
The channel lengths of the transistors are illustrated in
FIGS. 3A and 3B
to equal to each other. However, the channel length is different depending on whether the transistor is the driver transistor or the load transistor. Moreover, the channel length is different depending on whether the transistor is in the first stage, the second stage or the third stage. In
FIGS. 3A and 3B
, it should be noted that these transistors of the amplifier have different channel lengths and different channel widths sometimes but have the same structure in the vertical direction.
FIG. 4
shows a cross sectional view of the first stage transistor of the amplifier and the horizontal CCD section
102
in a charge transfer direction from the floating diffusion layer to a reset. The horizontal CCD section
102
is formed on an N-type embedded channel
116
as the charge transfer channel which is formed in the P-type well
111
on the N-type substrate
110
. Also, the horizontal CCD section
102
has the charge transfer electrode formed of a polysilicon film through the gate insulating film
114
. The gate insulating film
114
is sometimes composed of a multiple film (ONO film) in which an oxide film (SiO
2
) is formed in the either side of a nitride film (Si
3
N
4
). Also, the charge transfer electrode is sometimes formed of 2 polysilicon films.
The detection capacitor
108
as the floating diffusion layer capacitor is formed at an end portion of the horizontal CCD section
102
through the output gate OG. A high concentration N-type impurity layer is formed such that the signal charge stored in detection capacitor
108
can be taken out through a contact. A positive potential is given to a reset electrode &phgr;R after the charge detection, so that the signal charge is discharged to the reset drain
117
. Also, the potential of the floating diffusion layer is reset.
On the other hand, a drive transistor of an amplifier in the output section is formed as a MOS (Metal Oxide Semiconductor) type transistor. Each transistor has a drain region
113
and a source region
112
of high concentration N-type impurity regions formed in opposing positions of a P-type well
111
on an N-type substrate
110
. A gate electrode
115
of a polysilicon film is formed through a gate insulating film
114
. It should be noted that although not illustrated in
FIG. 4
, the vertical CCD section
105
has substantially the same structure as that of the horizontal CCD section
102
.
FIGS. 5A-1
and
5
A-
2
to
5
D-
1
and
5
D-
2
show the processes in the manufacturing method of the conventional solid state imaging apparatus. The figures with “−1” show the processes of the manufacturing method of the amplifier transistor of the first stage, and the figures with “−2” show the processes of the manufacturing method of the amplifier transistor of the second or third stage. The processes of the figures with “−1” are completely the same processes of the figures with “−2”. As mentioned above, in the conventional solid state imaging apparatus, all of these amplifier transistors have the same structure.
As shown in
FIGS. 5A-1
and
5
A-
2
, the P-type well
111
is first formed on the N-type substrate
110
and then the gate insulating film
114
is formed. An N-type embedded channel is already formed in a region where the vertical CCD and the horizontal CCD should be formed, although not illustrated. When an ONO film is
NEC Corporation
Wojciechowicz Edward
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