Test contact

Details Test contact Test contact

1999-02-26

2002-06-11

Le, N. (Department: 2858)

Electricity: measuring and testing

Fault detecting in electric circuits and of electric components

Of individual circuit component or element

Reexamination Certificate

active

06404216

ABSTRACT:

The present invention relates to semiconductor chip packages and leadframes, and more particularly to a technique for improving the test contact on leadframe fingers.
BACKGROUND OF THE INVENTION
Advances in semiconductor device technology have significantly increased the number of transistors that can be fabricated on a single semiconductor substrate. This increase in the number of transistors has had a corresponding decrease in transistor dimensions. Although semiconductor devices have decreased significantly in size, they still need to be interfaced with other devices. Semiconductor packaging schemes allow such interface. Examples of semiconductor packaging are Lead-On-Chip (LOC), and Dual-In-Line (DIP). In each of the packaging schemes, the resulting semiconductor device will reside in a package from which electrical leads will protrude. In turn the electrical leads will be affixed to a control board, such as a printed circuit board.
Prior to final affixation to a control board, it is desirable that the semiconductor devices be tested and burned-in. Post-fabrication testing and burning-in of packaged semiconductor devices is necessary to ensure proper performance of the devices. The use of leadframes allows a multitude of chips to be tested and burned-in. Leadframes are manufactured either by stamping the pattern for the leadframe from the leadframe material or by etching process. Traditionally leadframes are made of an iron system or copper system alloy that allows for durability and electrical conductivity. The base material is then coated with a Tin/Lead (Sn/Pb) plating. The Sn/Pb plating serves two purposes. First, the layer allows for easy soldering to a control board, since Sn/Pb is a typical soldering material. Second, the Sn/Pb plating is a soft material that allows for easy penetration of a test probe made of a harder material. Most test probes are made of a beryllium-copper base material, plated with a nickel, then gold coating. The penetration of the test probe into the soft plating creates a larger surface area for good electrical contact. The soft outer plating allows for a good ohmic and non-rectifying contact with the test probe, allowing accurate testing and efficient burn-in. A good contact will obey Ohm's law:
V=IR
where V is the voltage, I is the current and R is the resistance across the contact. Such a contact is in contrast to one where rectification between the contacting materials forms a region of high impedance such as a Schottky Barrier.
In recent years, particularly with the trend to move away from materials that contain lead, many leadframe manufacturers have used a nickel/palladium (Ni/Pd) plating on top of the base material. The Ni/Pd plating is a much harder material. While the Ni/Pd does not interfere with the soldering to a control board, it does not allow penetration of test probes into the material. The result is a bad electrical contact between the test probe and the leadframe legs, interfering with both proper electrical characterization and burn-in. In addition, the harder Ni/Pd layer wears the test probe surface, stripping the outer gold layer and decreasing the useful life of the probe.
SUMMARY OF THE INVENTION
In general, the invention provides an improved test contact surface for semiconductor tests and burn-in. In one aspect, a semiconductor leadframe is disclosed. The semiconductor leadframe includes a plurality of semiconductor chip mounting structures, which are arranged along a longitudinal axis, forming a long body; first and second guide rails, which are substantially parallel, formed at each side of the long body; and lateral support rails substantially perpendicular to the first and second guide rails and arranged between each of said chip mounting structures. Each of said mounting structures includes, fingers, having a top and bottom surface, for forming leads, the fingers connected to at least one of said first and second guide rails, and lateral support rails, a semiconductor chip mounting pad for mounting a semiconductor chip thereon, chip mounting pad supports for supporting the mounting pad, the chip mounting pad supports extending from the long body to the chip mounting pad, thereby supporting the chip mounting pad, test contacts on at least one of the top, and bottom surfaces of the fingers.
In another aspect, another embodiment of a semiconductor leadframe is disclosed. The semiconductor leadframe includes a plurality of semiconductor chip mounting structures, which are arranged along a longitudinal axis, forming a long body; first and second guide rails, which are substantially parallel and formed at each side of the long body; and lateral support rails substantially perpendicular to the first and second guide rails and arranged between each of the chip mounting structures. Each of the mounting structures includes, fingers, having a top and bottom surface, for forming leads, which are connected to at least one of said first and second guiderails; and the lateral support rails, where the fingers are adapted for receiving a semiconductor chip; and test contacts on at least one of the top and bottom surfaces of the fingers.
A semiconductor chip is attached to the die pad of the leadframe. Most of the leadframe and the chip is encapsulated in a semiconductor package. A molded carrier ring is formed around the leadframe for testing and handling. A test probe is put in contact with the test contacts for testing and burning-in the semiconductor chip.
In one implementation, the test contacts are made of a soft metal such as gold or silver.
In another aspect of the invention a method of manufacturing a semiconductor device assembly is disclosed. The method includes the steps of forming a semiconductor leadframe with a plurality of lead fingers; coating the leadframe with a hard, conductive material; and forming test contacts on said lead fingers.
In other implementations of the method, there are additional steps of mounting a semiconductor chip on the leadframe; encapsulating the,leadframe, the semiconductor chip, and a portion of said plurality of lead fingers in a semiconductor package; and placing a test probe on the test contacts.


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patent: 5451489 (1995-09-01), Leedy
patent: 5618404 (1997-04-01), Okuhama et al.
patent: 5623163 (1997-04-01), Izumi
patent: 5661337 (1997-08-01), Manteghi
patent: 5696033 (1997-12-01), Kinsman
patent: 5789280 (1998-08-01), Yokota
patent: 5789803 (1998-08-01), Kinsman
patent: 6034422 (2000-03-01), Horita et al.
patent: 6118286 (2000-09-01), Fredrickson

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