Semiconductor device manufacturing: process – Making device array and selectively interconnecting – With electrical circuit layout
Reexamination Certificate
2000-12-26
2002-12-10
Chaudhari, Chandra (Department: 2813)
Semiconductor device manufacturing: process
Making device array and selectively interconnecting
With electrical circuit layout
C438S620000, C438S622000, C438S599000
Reexamination Certificate
active
06492205
ABSTRACT:
BACKGROUND OF INVENTION
1) Field of the Invention
This invention relates generally to fabrication of semiconductor devices having macro cells, power lines and repeater cells and more particularly to the layout and method form placing repeater cell in between macro cells and modifying the power lines to place a Pin to the repeater cells in the power line areas between macro cells. Furthermore, the invention relates generally to fabrication and design of semiconductor devices and more particularly to the fabrication and design of power routing (VDD and VSS) and the location of buffer cells in macro cell areas.
2) Description of the Prior Art
The cells of a standard cell area normally contain a simple logic function, such as an inverter, a NAND gate, or a D-flip flop. The transistors in these cells are specifically designed for the drive requirements of the particular cell, and spacing of these transistors depends upon such factors as the location of contacts within the cells.
The spacing, or pitch, between rows of cells is determined by (a) the number of interconnect lines fabricated from METAL and (b) the cell height. The cell height, in turn, depends upon the transistor configuration within the cells.
The interconnect lines fabricated from METAL are typically laid out by an automated device, or computer program, called a “router,” or “auto-router.” Different routers have different algorithms for laying out the lines, so that different routers will produce different interconnect patterns, even though the end result of the connections may be the same.
Thus, in general, the row pitch is determined by (a) the router used to interconnect the cells in the standard cell array and (b) the height of the individual cells.
It is very important to efficiently arrange the wiring in an IC because, in general, the wiring running from transistor-to-transistor consumes more space than the transistors themselves. (The wiring consists of traces fabricated from the METAL layers) Restated, the size of the IC is generally determined by how efficiently the wiring can be routed and compacted, and not by how many transistors the IC contains.
Embedding MACROs into Standard Cell Arrays Uses Space
MACROs are frequently incorporated into ICs containing standard cell arrays. A MACRO is a block of transistors which have been optimized to perform a specific function. In a MACRO, the layout of the individual transistors, their operating characteristics, and their interconnections may have all been matched to each other for optimum performance. Thus, typically, a MACRO is constructed from different sizes of transistors, which are embedded into the standard cell array.
Since, in general, the ROW PITCH of the MACRO is different from that of the standard cell array, the power busses Vdd and Vss will be interrupted. To accommodate this interruption, the power busses are re-designed into a ring that surrounds a macro.
Power routing in today's SOC chips consumes a lot of chip area, especially for designs including many macro blocks such as SRAM, Flash and Mixed-Signal blocks. Usually a power ring needs to be routed around each of the macros in order to connect to all power pins of the macro. The result is that the area around the macros will be occupied by the power ring and no standard cells can be placed in that area.
For designs containing many macros the macros are often placed next to each other in groups. The spaces between the macros are used for power routing. The result is that the macro's and their surrounding power rings will form big areas on the chip in which no standard cells can be placed. Long nets which needs to be routed over these areas must therefore travel long distance without additional buffering (repeater), causing extensive signal delays.
The options available today are:
1) Create extra space between each macro to allow for standard cell rows to be placed. The buffer cells are then placed in these standard cell rows. This solution will sacrifice some area.
2) Route the net around the macro's. This will make it possible to insert additional buffers since the net will be routed over standard cell area. However, the net will be longer than routing across the macro's.
3) Use very high drive cells on the driver end of the net. This will improve net delay, but will have limited effect when the net reach a certain length.
The importance of overcoming the various deficiencies noted above is evidenced by the extensive technological development directed to the subject, as documented by the relevant patent and technical literature. The closest and apparently more relevant technical developments in the patent literature can be gleaned by considering U.S. Pat. No. 5,923,059(Gheewala) teaches a power routing (e.g., M1 M2- Vdd and Vss) that do not cross over macro cells.
U.S. Pat. No. 5,313,079(Brazen et al.) shows a gate array with flexible routing.
U.S. Pat. No. 5,869,900(Crafts) and U.S. Pat. No. 5,343,058(Shiffer, II) show related layouts and routings.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a method for fabricating and a design for power routing for semiconductor chips having macro areas
It is an object of the present invention to provide a method for fabricating and a design for power routing for semiconductor chips having macro areas where the buffer cells are inserted between the power lines over macro cell areas.
To accomplish the above objectives, the present invention provides a structure and method for forming buffer cells in power line areas between macro cell in a macro block area on a substrate. In a power line level, a pin is formed between VSS and VDD lines. The pin is connected to the buffer cell. Next a signal line layer is formed and the signal line is connected to the pin and to a driver. In a first embodiment the driver is formed in a standard cell area on the substrate. In a second embodiment, the driver is formed in a macro cell on a substrate.
The preferred first embodiment of the invention provides a method of fabrication of buffer cells in power line areas between macro cells in a macro area in a semiconductor device. The invention's buffer cell is in a power line area
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within a macro area. A key feature of the first embodiment is the placement of the buffer cell in the power line area within a macro area. In contrast, normally, buffer cells are located in the standard cell area or in the macro cell areas.
The second embodiment has a weak driver in a macro cell. Like the first embodiment, the buffer cell is in the power line area. The pin is electrically connected to the buffer cell. The signal line is connected to the drive and the pin this is connected to the buffer cell.
The two embodiments of the present invention provide the following benefits.
1. A way of utilizing power routing area for buffer insertion
2. A way of saving total chip area
3. A way of decreasing signal delays for long nets
4. A way of generating special cell layout fit to be placed under power lines.
5. A way of placing cells under power lines.
By using the invention's special buffer cells, which are laid out so that it can be placed under the power lines and by placing, these buffer cells in the power line area between the macros, signals that travel long distance across macro areas can repeated. This will decrease the signal delay for long wires crossing macro areas and improve overall design performance without sacrificing area.
Additional objects and advantages of the invention will be set forth in the description that follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objects and advantages of the invention may be realized and obtained by means of instrumentalities and combinations particularly pointed out in the append claims.
REFERENCES:
patent: 5313079 (1994-05-01), Brasen et al.
patent: 5343058 (1994-08-01), Shiffer, II
patent: 5619048 (1997-04-01), Yokota et al.
patent: 5869900 (1999-02-01), Crafts
patent: 5923059 (1999-07-01), Gheewala
patent: 6091090 (2000-07-01),
Chen Chien-Wen
Liu Louis Chao-Chiuan
Chaudhari Chandra
Hogans David
Stoffel William J.
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