Coded data generation or conversion – Converter calibration or testing
Reexamination Certificate
2001-04-25
2002-11-26
Young, Brian (Department: 2819)
Coded data generation or conversion
Converter calibration or testing
C341S155000
Reexamination Certificate
active
06486807
ABSTRACT:
BACKGROUND
The present invention relates to A/D converters (analog-to-digital converters), and in particular to calibration of a pipeline stage in a multi-bit/stage pipeline A/D converter.
The maximum achievable accuracy-speed performance of any A/D-converter is limited by non-ideal effects associated with its building blocks. Typically, the performance is limited by settling time, finite amplifier gain and/or analog component mismatch. When designing high-speed, high-accuracy A/D converters, these limitations impose very stringent demands on the building blocks, leading to prolonged design time. They also require the use of manufacturing processes that are optimized for component matching, thus increasing the manufacturing cost. This is the motivation for finding A/D converter architectures that will relax such design-requirements.
The influence of component mismatch can be reduced in several ways. Examples of prior art solutions are given below. References [1]-[2] disclose pipeline A/D converter algorithms that automatically correct erroneous bit-level decisions caused by component mismatch. This helps to reduce the requirements on the components that are involved in the bit-level decisions, i.e., the comparator and reference circuit. This technique is often called digital correction. However, such digital correction methods for pipeline A/D converters are limited in that they only compensate for errors in the sub A/D converters (internal low-resolution A/D converters) but not for errors in the multiplying D/A converters (internal low-resolution D/A converters). Reference [3] suggests random selection of components. This transforms the error into noise, so that the components match perfectly “in average”. This technique is also called dynamic element matching or scrambling. Dynamic element matching does not actually reduce the error energy, it is just spread out over the entire frequency spectrum. This helps to improve the SFDR (Spurious-Free Dynamic Range), but the SINAD (SIgnal-to-Noise-And-Distortion ratio) is unaltered, and therefore the effective resolution of the A/D converter is not improved. Only if the signal band of interest is less than the Nyquist band, can the in-band SINAD be improved by spectral shaping of the random signal, see [4].
Another prior art technique to reduce component mismatch is trimming of on-chip components. Each critical analog component is trimmed to improve matching beyond the tolerances of the manufacturing process, e.g. as disclosed in [5]. However, trimming is a costly extra manufacturing step. Furthermore, trimming is only performed at one specific operating condition that has to cover all future conditions.
A further prior art technique to reduce the impact of component mismatch on performance is some form of calibration in the analog or digital domain. Generally, a calibration algorithm first acquires information representing the imperfections of the circuit, and then subtracts the estimated error, either in the analog [6]-[7] or the digital domain [8]. Generally, calibration methods that subtract errors in the analog domain have to rely again on analog component matching, and are therefore likely to be sub-optimal. Calibration methods that subtract errors in the digital domain do not suffer from such limitations.
Several digital domain calibration methods have been proposed.
One approach is to have a very pure or otherwise known reference input signal, analyze the distortion from the conversion process, and then correct the transfer function of the A/D converter [9]-[10].
Another digital calibration method is to use a “golden” A/D converter or D/A converter as a high-precision reference, then compare the imperfect A/D converter output at a certain code with the “golden” value and establish the difference as a code-dependent error to be corrected. This is the approach in [11]-[12]. While potentially giving good results, using a “golden” reference is not desirable in many situations. Clearly it is preferable that the A/D converter can calibrate itself without the need for external or internal high-precision references.
Examples of digital calibration for 1-bit/stage and 1.5-bit/stage pipeline A/D converters are also found in [13]-[14] and [15]-[17], respectively, and for multi-bit/stage A/D converters in [18]-[19]. Common to all of these converters is that the internal D/A converter is forced through a calibration sequence, and the resulting analog output is digitized and processed to extract information about the conversion error.
The solutions proposed for 1 bit and 1.5 bit/stage pipeline A/D converters are, however, not suitable for calibration of multi-bit/stage architectures.
The multi-bit/stage solutions use code-related calibration, which means that the calibration coefficient is associated with the occurrence of a certain code. This leads to several drawbacks:
The calibration coefficient is associated with each code of the first, or first few, internal D/A converters, thus correcting for the sum of unit-segment errors associated with each code. However, even after calibration there will be a residual error that was not removed by the calibration. Due to drift, there will also be small changes in how effective the calibration is. All of this will lead to incomplete removal of the harmonic distortion. This residual distortion could be removed by applying dynamic element matching (random selection of which m unit-segments are used to represent a code m). There are, however, a large number of valid ways to select m unit-segments out of n, especially in the middle of the code range. The code-related calibration coefficients in the prior art cover only one pre-determined set of m unit-segments representing code m, and can therefore not be used together with dynamic element matching or any other form of random or deterministic scrambling of the D/A converter unit-segments.
Furthermore, in prior art multi-bit/stage pipeline A/D converters the D/A converter is switched through its range of codes starting either from one end or the other [18], or from the middle of the code-range [19]. The error for each unit-segment is then identified as the error in the incremental output change between two adjacent D/A converter codes. Due to the inter-stage gain, the analog output would for most codes be well out of range for the remaining pipeline stages unless an appropriate input value is sampled as well. The sampling of such an input signal introduces a code-dependent charge feed-through error in SC (Switched Capacitor) implementations, and should be avoided.
Another drawback in prior art multi-bit/stage pipeline A/D converters is that the calibration coefficients for each code are calculated by accumulating the estimated unit-segment errors measured up to that code, see [18]-[19]. However, this implies that the estimation errors for each unit-segment are accumulated as well, which leads to different precision in the estimation of the first and last coefficients.
SUMMARY
It is an object of the present invention to accurately detect and compensate for circuit imperfections in A/D converters using hardware that is itself subject to the same, or equivalent, imperfections. More specifically, the invention is concerned with the problem of extracting and using such information for calibration of multi-bit/stage pipeline A/D converters without hindering the use of further performance enhancement techniques, such as dynamic element matching.
This object is achieved in accordance with the attached claims.
Briefly, the present invention calibrates a pipeline stage by switching a unit-segment in the D/A converter of the pipeline stage between its two complementary states and calculating the difference between the resulting digital signals produced by the A/D converter. In this switching process the remaining unit-segments of the pipeline sta
LandOfFree
A/D converter calibration does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with A/D converter calibration, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and A/D converter calibration will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2943811