Memory module having buffer for isolating stacked memory...

Details Memory module having buffer for isolating stacked memory... Memory module having buffer for isolating stacked memory...

2000-09-18

2002-11-26

Hoang, Huan (Department: 2818)

Static information storage and retrieval

Format or disposition of elements

C365S052000, C365S063000

Reexamination Certificate

active

06487102

ABSTRACT:

BACKGROUND OF THE INVENTION
FIG. 1
is a block diagram of a prior art memory system. The system of
FIG. 1
includes three memory modules
10
,
12
, and
14
that are coupled to a memory controller
16
through a bus
18
. Each memory module is fabricated on a circuit board that plugs into a connector
20
on a mother board
22
. Each module includes multiple memory devices
24
,
26
, and
28
that are coupled to the bus
18
to allow the memory controller to access the memory devices.
To increase the memory density of the modules, memory devices can be stacked on top of each other, thereby increasing the memory capacity of each module without increasing the space required on the circuit board. Stacking memory devices, however, increases the capacitive loading of the signals on the bus. For example, from the perspective of the memory controller
16
, each data line in the bus
18
has a total capacitance that equals the sum of the capacitance of each portion of the signal line running through sections A, B, and C of the bus, plus the capacitance of the portion of the data line in sections
30
,
32
, and
34
that couple the memory devices to the bus, plus the sum of the input capacitance of all of the memory devices (which are attached to sections
30
,
32
, and
34
in parallel). If additional memory devices are stacked on devices
24
,
26
, and
28
, then the capacitance of the additional devices are added to the total capacitance seen by the controller. Therefore, when the memory controller drives a data signal onto the bus, it must overcome the combined capacitance of all of the stacked memory devices. This heavy capacitive loading reduces the maximum operating speed and increases the power consumption by the memory system, especially at higher operating frequencies.


REFERENCES:
patent: 5517057 (1996-05-01), Beilstein et al.
patent: 5581498 (1996-12-01), Ludwig et al.
patent: 5943254 (1999-08-01), Bakeman et al.
patent: 5953215 (1999-09-01), Karabatsos
patent: 5963716 (1999-10-01), Welborn et al.

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