Semiconductor device comprising transistor

Details Semiconductor device comprising transistor Semiconductor device comprising transistor

2000-03-06

2002-02-05

Wilson, Allan R. (Department: 2815)

Active solid-state devices (e.g., transistors, solid-state diode

Bipolar transistor structure

With base region having specified doping concentration...

C257S587000

Reexamination Certificate

active

06344678

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device comprising a transistor, and more particularly, it relates to a semiconductor device comprising a transistor capable of suppressing dispersion of the current amplification factor of the transistor.
2. Description of the Prior Art
An exemplary conventional semiconductor device comprising transistors employed for diving/controlling a motor or an air bag for a car, for example, is described. In this type of semiconductor device, a bipolar transistor and MOS transistors are formed on the same semiconductor substrate. The structure of a portion forming the bipolar transistor is now described.
Referring to
FIG. 12
, an n
−
epitaxial layer
4
is formed on a p-type silicon substrate
1
. An n
+
diffusion layer
2
a
and a p
+
diffusion layer
3
are formed between the p-type silicon substrate
1
and the n
−
epitaxial layer
4
. A p
+
diffusion layer
5
a
and LOCOS oxide films
6
for electrically isolating this portion from another element region (not shown) are formed on the n
−
epitaxial layer
4
.
A p diffusion layer
6
is formed on the surface of the n
−
epitaxial layer
4
and in the vicinity thereof. An n
−
diffusion layer
8
b
and an n
+
diffusion layer
9
b
are formed on the surface of the p diffusion layer
7
and in the vicinity thereof. A p
+
diffusion layer
100
for attaining contact with the p diffusion layer
7
is formed on the p diffusion layer
7
.
Further, an n
−
diffusion layer
8
a
and an n
+
diffusion layer
9
a
for attaining contact with the n
−
epitaxial layer
4
are formed on the surface of the n
−
epitaxial layer
4
and in the vicinity thereof.
The n
−
epitaxial layer
4
defines a collector region in the bipolar transistor, the p diffusion layer
7
and the p
+
diffusion layer
100
define a base region, and the n
−
diffusion layer
8
b
and the n
+
diffusion layer
9
b
define an emitter region.
An interlayer insulation film
11
is formed to cover the p diffusion layer
7
and the LOCOS oxide films
6
. A contact hole
12
a
exposing the surface of the n
+
diffusion layer
9
a
is formed in the interlayer insulation film
11
. Further, a contact hole
12
b
is formed to expose the surface of the p
+
diffusion layer
100
. In addition, a contact hole
12
c
is formed to expose the surface of the n
+
diffusion layer
9
b.
A collector electrode
13
a
electrically connected with the n
+
diffusion layer
9
a
is formed in the contact hole
12
a.
A base electrode
13
b
electrically connected with the p
+
diffusion layer
100
is formed in the contact hole
12
b.
An emitter electrode
13
c
electrically connected with the n
+
diffusion layer
9
b
is formed in the contact hole
12
c.
Other semiconductor elements such as MOS transistors are formed on another element forming region (not shown) electrically isolated from this region formed with the bipolar transistor by the LOCOS oxide films
6
and the like.
A method of fabricating the semiconductor device having the aforementioned bipolar transistor is described along with a method of fabricating MOS transistors. Referring to
FIG. 13
, prescribed n
+
diffusion layers
2
a
and
2
b,
the p
+
diffusion layer
3
and the n
−
epitaxial layer
4
are formed on the p-type silicon substrate
1
. Phosphorus is injected into a prescribed region of the n
−
epitaxial layer
4
, thereby forming an n
−
diffusion layer
14
for forming a p-channel MOS transistor.
Further, boron is injected into other prescribed regions of the n
−
epitaxial layer
4
, thereby forming a p
+
diffusion layer
5
b
for forming an n- channel MOS transistor and a p
+
diffusion layer
5
a
for element isolation.
Then, the LOCOS oxide films
6
are formed on prescribed regions of the n
−
epitaxial layer
4
. A gate electrode
19
a
formed by a polysilicon film
16
a
and a tungsten silicide film
17
a
is formed on the n
−
diffusion layer
14
through a gate insulator film
151
a.
At the same time, a gate electrode
19
b
formed by a polysilicon film
16
b
and a tungsten silicide film
17
b
is formed on the p
+
diffusion layer
5
b
through a gate insulator film
151
b.
Then, boron is injected into a prescribed region of the n
−
epitaxial layer
4
, thereby forming the p diffusion layer
7
partially forming the base region of the bipolar transistor.
The gate electrode
19
b
and a prescribed photoresist pattern (not shown) are employed as masks for injecting a prescribed impurity, thereby forming the n
−
diffusion layers
8
a
and
8
b
and n
−
diffusion layers
8
c
and
8
d
respectively. Side wall insulator films
18
a
are formed on both side surfaces of the gate electrode
19
a,
and side wall insulator films
18
b
are formed on both side surfaces of the gate electrode
19
b.
The gate electrode
19
b,
the side wall insulator films
18
b
and a prescribed photoresist pattern
200
are employed as masks for injecting a prescribed impurity, thereby forming the n
+
diffusion layers
9
a
and
9
b
and n
+
diffusion layers
9
c
and
9
d
respectively.
Referring to
FIG. 14
, the photoresist pattern
200
is removed and heat treatment is performed in a nitrogen atmosphere. Referring to
FIG. 15
, a photoresist pattern
202
exposing part of the surface of the p diffusion layer
7
and the surface of the n
−
diffusion layer
14
is formed on the n
−
epitaxial layer
4
.
The photoresist pattern
202
is employed as a mask for injecting a prescribed impurity, thereby forming the p
+
diffusion layer.
100
on the surface of the p diffusion layer
7
and in the vicinity thereof. P
+
diffusion layers
10
b
and
10
c
are formed on the n
−
diffusion layer
14
. Thereafter the photoresist pattern
200
is removed.
Thus formed is a bipolar transistor T
1
having the collector region defined by the n
−
epitaxial layer
4
, the base region defined by the p diffusion layer
7
and the p
+
diffusion layer
100
and the emitter region defined by the n
−
diffusion layer
8
b
and the n
+
diffusion layer
9
b.
Further, a p-channel MOS transistor T
2
is formed with source/drain regions defined by the p
+
diffusion layers
10
b
and
10
c.
In addition, an n-channel MOS transistor T
3
is formed with source/drain regions defined by the n
−
diffusion layers
8
c
and
8
d
and the n
+
diffusion layers
9
c
and
9
d
.
Referring to
FIG. 16
, the interlayer insulating film
11
formed by a silicon oxide film, for example, is formed on the n
−
epitaxial layer
4
by CVD or the like. A prescribed photoresist pattern (not shown) is formed on the interlayer insulating film
11
.
The photoresist pattern is employed as a mask for anisotropically etching the interlayer insulating film
11
, thereby forming the contact holes
12
a,
12
b
and
12
c
and contact holes
12
d,
12
e,
12
f
and
12
g
respectively. Thereafter the electrodes
13
a
to
13
c
and prescribed electrodes
13
d
to
13
g
are formed in the contact holes
12
a
to
12
g
respectively.
A principal part of the semiconductor device comprising the bipolar transistor T
1
and the MOS transistors T
2
and T
3
is completed through the aforementioned steps.
However, the semiconductor device obtained in the aforementioned method has the following problem: When evaluating collector current dependency of a current amplification factor h
FE
particularly in the bipolar transistor T
1
in the aforementioned semiconductor device, the current amplification factor h
FE
proved to remarkably disperse in the wafer plane. This problem is now described.
FIGS. 17B
to
17
F are graphs showing values of the current amplification factor h
FE
of the bipolar transistor T
1
evaluated on five points of the wafer plane shown in
FIG. 17A
respectively. It

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