Semiconductor device manufacturing: process – Making passive device – Stacked capacitor
Reexamination Certificate
1999-04-08
2002-06-11
Meier, Stephen D. (Department: 2822)
Semiconductor device manufacturing: process
Making passive device
Stacked capacitor
C438S253000, C438S254000, C438S397000
Reexamination Certificate
active
06403440
ABSTRACT:
BACKGROUND OF THE INVENTION
Field of the Invention
The present invention relates to a method for fabricating a stacked capacitor in a semiconductor configuration in which one electrode of the stacked capacitor is connected via a terminal region of a first conductivity type to a source or drain of a transistor. The one electrode of the stacked capacitor is produced by utilizing different etching rates of semiconductor layers of a second conductivity type which are doped to different extents. In addition, the present invention relates to a stacked capacitor fabricated by this method.
The terms p-doped, p
+
-doped, p
−
-doped, n-doped, n
+
-doped, n
−
-doped are used synonymously with the abbreviations p-type, p
+
type, p
+
-type, p
−
-type, n-type, n
+
-type, n
−
-type, as is customary among those skilled in semiconductor technology.
In the case of a method for fabricating a DRAM cell configuration as disclosed in Published, Non-prosecuted German Patent Application DE 195 26 952 A1, a storage capacitor is disposed in a trench and includes an electrode structure with a plurality of elements with a bulbous configuration and whose surface is provided with a storage dielectric and a counter-electrode. The electrode structure is fabricated by employing the etching of p
−
-doped polysilicon, which etching is selective with respect to p
+
-doped polysilicon. Therefore, the fact that p
−
-doped polysilicon can be etched significantly more rapidly (by a factor of the order of magnitude of 100) compared with p
+
-doped polysilicon is utilized in this case. In the case of the fabrication of a trench-type storage capacitor disclosed in U.S. Pat. No. 5,153,813, dry etching is performed with alternately oppositely doped semiconductor layers, and the fact that the oppositely doped semiconductor layers have different etching rates is utilized in the process. In this way, the surface and hence the capacitance of the capacitor is enlarged.
U.S. Pat. No. 5,637,523 discloses a method in which, in order to enlarge the capacitor area of a stacked capacitor disposed on a semiconductor body, the capacitor is formed from alternately disposed first and second semiconductor layers, which can be etched differently. Examples of these layers are amorphous or polycrystalline silicon having different doping concentrations.
U.S. Pat. No. 5,053,351 describes a method for fabricating a stacked capacitor for a DRAM cell. In the DRAM cell polycrystalline layers and dielectric layers are applied alternately to a semiconductor body and in which the dielectric layers are then removed in a selective etching step, in order in this way to obtain a capacitor area which is as large as possible.
Finally, German Patent DE 195 46 999 C1 discloses a method for fabricating a stacked capacitor on a semiconductor body provided with a transistor, in which, in a manner similar to that in the method disclosed in Published, Non-prosecuted German Patent Application DE 195 26 952 A1, the selective etchability of p
+
-doped polysilicon and p
−
-doped polysilicon is utilized in order to produce a lamellar electrode of the stacked capacitor.
On account of the high selective etchability of p
+
-type polysilicon and p
−
-type polysilicon, the last-mentioned method has proved to be particularly successful for producing lamella or laminar structures made of p
+
-type polysilicon, which is used as the first electrode of the stacked capacitor. In the known method, the electrode firstly has applied to it a dielectric (silicon oxide and/or silicon nitride and/or ON or else ONO etc.), after which the counter-electrode is then formed.
The known method, which is extremely expedient for fabricating a stacked capacitor, has a serious disadvantage, however, for the function of a memory cell using the stacked capacitor. The contact-making of the inner electrode of the stacked capacitor, which electrode is inevitably p
+
-conducting on account of the etching process, with the source/drain terminal region of the transistor provided in the semiconductor body, which terminal region is n
+
-conducting for other reasons, is not directly possible. This is because the p
+
n
+
junction present in this case forms a diode that severely impairs or even completely prevents the functioning of the DRAM cell. For this reason, a concept has been conceived of heretofore which envisages providing a metallic intermediate layer between the n
+
-conducting source/drain terminal region of the transistor and the p
+
-conducting electrode of the stacked capacitor, which ensures a resistive connection between the terminal region and the electrode. Although this makes it possible to provide for entirely satisfactory functioning of the memory cell, the introduction of the metallic intermediate layer, which is buried in the layer structure, has turned out to be problematic, since the rest of the process for fabricating the stacked capacitor is thereby altered and requires process variants which have not been able to be resolved heretofore. Even though, therefore, the utilization of the etching selectivity between p
+
-type polysilicon and p
−
-type polysilicon is desirable in the fabrication of a stacked capacitor, it has not been possible to date to solve the problems arising with the p
30
n
30
junction between the internal p
+
-type electrode of the stacked capacitor and the n
+
-type source/drain terminal region, which p
30
n
30
junction inevitably occurs in the case of n-channel transistors. Therefore, it has not been possible to date to successfully fabricate stacked capacitors in the context of n-channel transistors by utilizing the selective etchability of p
+
-type polysilicon and p
−
-type polysilicon.
SUMMARY OF THE INVENTION
It is accordingly an object of the invention to provide a method for fabricating a stacked capacitor in a semiconductor configuration, and a stacked capacitor fabricated by the method that overcome the above-mentioned disadvantages of the prior art methods and devices of this general type, which utilizes the selective etchability of p
+
-type polysilicon and p
−
-type polysilicon and can readily be used with n-channel transistors; in addition, the intention is to provide a stacked capacitor fabricated by the method.
With the foregoing and other objects in view there is provided, in accordance with the invention, a method for fabricating a capacitor in a semiconductor configuration, which includes: providing a transistor with a source/drain region formed in a semiconductor body and a terminal region of a first conductivity type connected to the source/drain region; applying alternating semiconductor layers of different doping concentrations of a second conductivity type including weaker doped layers and stronger doped layers on the terminal region resulting in the alternating semiconductor layers having different etching rates for forming one electrode of a stacked capacitor connected to the terminal region; etching the alternating semiconductor layers resulting in selective removal of some of the alternatively semiconductor layers for forming the one electrode of the stacked capacitor from remaining layers of the alternating semiconductor layers; and performing a doping reversal of the remaining layers remaining after the etching step to the first conductivity type for forming the one electrode of the stacked capacitor.
In the case of the method of the type mentioned in the introduction, the object is achieved according to the invention by virtue of the fact that after the etching of the one electrode of the stacked capacitor, doping reversal of the semiconductor layers remaining after the etching operation to the first conductivity type is performed.
The invention thus follows a path that departs completely from the previous prior art. Instead of adopting special metalizations or measures for ruling out the disadvantages associated with the p
30
n
30
junction which is in
Bertagnolli Emmerich
Willer Josef
Brophy Jamie L.
Meier Stephen D.
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