Semiconductor device manufacturing: process – With measuring or testing
Reexamination Certificate
2000-08-24
2002-06-11
Picardat, Kevin M. (Department: 2822)
Semiconductor device manufacturing: process
With measuring or testing
C438S004000, C438S016000, C324S750010, C324S754120
Reexamination Certificate
active
06403386
ABSTRACT:
FIELD OF THE INVENTION
The present invention generally relates to a method and apparatus for identifying failure sites on IC chips by a liquid crystal method and more particularly, relates to a method and apparatus for identifying failure sites on IC chips by a liquid crystal/glass substrate which is positioned in intimate contact with a top surface of an IC chip with the liquid crystal layer heated to a temperature just below its transition temperature such that any shorts or leakages in the IC chip will heat up the immediately adjacent liquid crystal material to pass its transition temperature and thus revealing a hot spot for identifying the failure site.
BACKGROUND OF THE INVENTION
In the semiconductor fabrication technology, the capability and effectiveness of performing a failure analysis on a semiconductor chip package are very important. When an integrated circuit (IC) chip fails in service the nature and the cause for such failure must be determined in order to prevent the reoccurrence of such failure in similar products.
An IC chip is normally built on a silicon base substrate with many layers of insulating materials and metal interconnections. This type of multi-layer structure becomes more important in modern IC devices such as high density memory chips where, in order to save chip real estate, the active device is built upwards in many layers forming transistors, capacitors and other logic components.
When an IC device is found defective during a quality control test, various failure analysis techniques can be used to determine the cause of such failure. Two of the more recently developed techniques for performing failure analysis are the infrared light emission microscopy and the light-induced voltage alteration (LIVA) imaging technique. In the infrared light emission light analysis, an infrared light transmitted through a substrate silicon material is used to observe from the backside of an IC the failure mode of the circuit. For instance, at a magnification ratio of 100×, a failure point in the circuitry can be located. The LIVA imaging technique can be used to locate open-circuited and damaged junctions and to image transistor logic states. The LIVA images are produced by monitoring the voltage fluctuation of a constant current power supply when a laser beam is scanned over an IC. A high selectivity for locating defects is possible with the LIVA technique.
Another method that has become more common in failure analysis of IC chips is the scanning optical microscopy (SOM). The high focusing capability of SOM provides improved image resolution and depth comparable to conventional optical microscopy. It is a useful tool based on the laser beam's interaction with the IC. The SOM technique enables the localization of photocurrents to produce optical beam induced current image that show junction regions and transistor logic states. Several major benefits are made possible by the SOM method when compared to a conventional scanning electron microscopy analysis. For instance, the benefits include the relative ease of making IC electrical connection, the no longer required vacuum system and the absence of ionizing radiation effects.
Even though the above discussed techniques are effective in identifying failure modes in IC circuits, the techniques require elaborate and complicated electronic equipment which are generally costly and not readily available in a semiconductor fabrication facility. It is therefore desirable to have available a method and apparatus that can be easily carried out without expensive laboratory equipment and thus the apparatus can be installed in any fabrication facilities. One of such methods is the use of a liquid crystal coating layer for the identification of failure sites in an IC chip. For instance, in a conventional method wherein a liquid crystal layer is used for the identification of failure sites, a liquid crystal material is frequently coated on top of an IC chip or an IC package. A typical set up is shown in FIG.
1
.
As shown in
FIG. 1
a typical liquid crystal detection apparatus
10
is provided. The apparatus
10
generally includes a heater
12
and an optical microscope
14
. On a top surface
16
of the heater
12
, an IC package
20
is positioned under the microscope
14
The IC package
20
may be a plastic quad flat pack (PQFP) or any other packaged IC device. The IC package
20
, shown in
FIG. 1
, is completed with bonding pads
22
and bonding wires
24
. In the middle portion of the package
20
are IC circuits that contain failure sites need to be identified by a liquid crystal method. In the conventional method, a liquid crystal material is first coated to the top surface
26
of the IC package
20
. The IC package
20
is then positioned in top of the heater
12
which can be heated at a pre-programmed heating rate to a specific temperature. The IC package
20
, together with the coated liquid crystal layer (not shown) is normally heated to a temperature just below the clear/opaque transition temperature of the liquid crystal material. For instance, a suitable temperature would be approximately between about 5° and about 10° below the transition temperature of the liquid crystal. After the IC package
20
is heated to such predetermined temperature, a pre-selected voltage is applied to the IC circuit through bonding wires
24
. The IC circuit, upon receiving such a voltage, heats up at any short or leakage positions. A hot spot is thus generated at each of such locations. The liquid crystal material immediately adjacent, or contacting such hot spots therefore has its temperature raised above its transition temperature and transforms from an opaque state to a clear state. As a result, bright spots in the liquid crystal layer, i.e., on the IC package, show up to indicate the failure sites in the package.
Several drawbacks have been noted in the practice of the above described conventional method. First, a new coating of a liquid crystal material must be applied to each IC package or each IC chip to be examined under the microscope. The liquid crystal material once applied, is not reusable. i.e., cannot be transferred to another IC device. The coating and the drying process for the liquid crystal material for each IC package to be examined increase the complexity of the method. Secondly, the entire IC package, or the IC chip must be heated on the heater in order to bring the temperature of the liquid crystal coating layer to just below its transition temperature. Due to the large mass of the material to be heated, the exact temperature of the IC package is not only difficult to control but also requires a long time for heating to such temperature. Furthermore, the IC package requires a long time to cool once the temperature is heated passing its transition temperature. This further requires longer processing time
It is therefore an object of the present invention to provide a method for identifying failure sites on a defective IC chip that does not have the drawbacks and shortcomings of the conventional method of using liquid crystal material.
It is another object of the present invention to provide a method for identifying failure sites on a defective IC chip by utilizing a reusable liquid crystal apparatus such that each IC chip to be tested does not require a separate coating of a liquid crystal material.
It is a further object of the present invention to provide a method for identifying failure sites on a defective IC chip by utilizing a liquid crystal apparatus constructed by coating a liquid crystal material on a substantially transparent substrate.
It is another further object of the present invention to provide a method for identifying failure sites on a defective IC chip by utilizing a liquid crystal apparatus wherein a substrate equipped with heating elements is coated with a liquid crystal material to form a reusable liquid crystal apparatus.
It is still another object of the present invention to provide a method for identifying failure sites on a defective IC chip by utilizing a liquid crystal a
Picardat Kevin M.
Taiwan Semiconductor Manufacturing Co. Ltd
Tung Randy W.
LandOfFree
Method and apparatus for identifying failure sites on IC chips does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method and apparatus for identifying failure sites on IC chips, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and apparatus for identifying failure sites on IC chips will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2940223